FEATURE: TEST & MEASUREMENT
PUMPING UP THE PIC VOLUME
There are many challenges to overcome to provide quick and efficient characterisation of photonic integrated circuits
ANDY EXTANCE
T
oday the internet is the fastest it has ever been – but that achievement brings enormous optical communication testing challenges.
Tat’s underlined by Jeroen Duis, chief commercial officer of Phix Photonics Assembly in Enschede, Netherlands, which performs hybrid integration of chips, assembling multiple chips into a single package. ‘Customers would like to have a transmission test to validate that the whole module is working correctly,’ he explained, adding that test systems cost hundreds of thousands, or millions, of dollars. Tat value disappears in two or three years as communication speeds accelerate, Duis said. Tese tests should reveal the number of
bit errors, resulting in signals producing false zeroes or ones in the digital domain. But low error rates and the greater functionality of transceivers have lengthened testing, requiring more time to collect sufficient error data. ‘Typically, the testing is four to eight minutes per product in a volume environment,’ Duis explained. Consequently, when manufacturing
10 FiBRE SYSTEMS n Issue 25 n Autumn 2019
scales up, expensive but short-lived test systems ‘need to be duplicated and operated in parallel,’ he added, creating regular significant expenses. Such challenges intensify with photonic
integrated circuits (PICs), currently made in fairly small volumes. Yet these are the same devices delivering vital technical advances. Terefore, PICs must be made on a larger scale. Contract manufacturing companies such as Phix, equipment makers, universities and industry groups are therefore coming together to develop test and measurement technology and standards to enable that.
Step-by-step Testing could be done at various steps of manufacturing, Duis explained, including analysing deposition and etching to achieve full statistical process control at the wafer level. ‘However, this works only in continuous high- volume manufacturing,’ he said. ‘Most photonic chips are made in batches with small quantities.’ Typically, the first optical tests are only done
aſter fabricating PICs, when semiconductor wafers have been diced to form chips. A first verification step reveals whether a design and/ or process can meet expectations. If the chip fails it must be excluded, whether the problem is with chip design or the manufacturing process. ‘Aſter the issue is found, one needs to correct for this, and start a rerun, which easily pushes delivery back four months,’ Duis said. Sylwester Latkowski, from the Photonic
Integration Technology Centre, at Eindhoven University of Technology (TU/e) in the Netherlands, notes that things can be simpler once verification is complete. ‘It is, in general, cheaper if we can detect known-good-die (KGD) as early as possible in the production chain,’ he said. ‘Only then can we take adequate countermeasures to optimise cost of production.’ Validating dies to prevent faulty ones entering the supply chain cuts costs and frees up capacity. If some chips can’t deliver at full expected specification, they could perhaps be repurposed, Latkowski added. Wafers might also be discarded before dicing, if testing
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