FEATURE Robotics & Motion Control y
Figure 4. Frame latencies: (a) 2-port node frame latencies and (b) line end node.
with data on the wire are fixed and related to the bit rate, utilising low latency components, such as the ADIN1200 PHY and the fido5000 embedded switch, is key to performance optimisation, especially as node count increases (for example, 12-axis CNC machine) and cycle times reduce. Moving to gigabit Ethernet dramatically reduces the impact of bandwidth delay, but increases the proportion of overall latency introduced by the switch and PHY components. For example, a 12-axis CNC machine on a gigabit network will have a network transmission delay of approximately 7.5 µs. The bandwidth element of this is negligible, and it makes little difference whether minimum or maximum Ethernet frame sizes are used. The network delay is split approximately equally between the PHYs and the switches, underlining the value in minimising the latency in these elements as industrial systems move toward gigabit speeds, control cycle times reduce (EtherCAT has demonstrated 12.5 µs cycle times), and node count expands with the addition of Ethernet connected sensors in the control network and the flattening of network topologies.
Figure 5. Frame transmission timeline.
deterministic time-sensitive applications. The latencies introduced by the PHY
and switch are listed in Table 1, assuming that the receive buffer analysis is destination address based and assuming a 100 Mbps network. As an example, aggregating these delays
up to a 7-axis line network, and including the clocking of the full payload into the final node (3a in Figure 4), the total transmission delay becomes
This calculation assumes that there is no where the 58 × 80 ns represents the
remaining 58-byte payload after the preamble and destination address bytes have been read.
other traffic on the network or that the network is managed to enable priority access for time sensitive traffic. It is also somewhat protocol dependent, with slight variations in the calculation being introduced depending on the exact Industrial Ethernet protocol used. Referring back to Figure 2, in a machine system with cycle times down to 50 µs to 100 µs, the frame transmission to the furthest node can take up to almost 50% of the cycle, reducing the time available to update the motor control and motion control algorithm calculations for the next cycle. Minimising this transmission time is important for performance optimisation, as it allows longer and more complex control calculations. Given that delays associated
Conclusion
In high performance, multiaxis, synchronised motion applications, control timing requirements are precise, deterministic, and time critical, with a requirement to minimise end-to-end latency, especially as control cycle times get shorter and control algorithm complexity increases. Low latency PHYs and embedded cut- through switches are important elements in optimising these systems. To address the challenges outlined in this article, Analog Devices has recently released two new robust Industrial Ethernet PHYs, the ADIN1300 (10 Mb/100 Mb/1 Gb) and ADIN1200 (10 Mb/100 Mb).
CONTACT:
Analog Devices Web:
www.analog.com
Table 1. PHY and Switch Latencies
automationmagazine.co.uk Automation | June 2020 23
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