EDITOR’S CHOICE
At the same time, LOs/VCOs see constant load but require critical high accuracy and low noise. The high bandwidth feature of LT8625SP enables designers to power the two critical 1V load groups from a single IC by separating the dynamic load and static load with a second inductor (L2). Figure 2 shows the output voltage response with a 4A to 6A dynamic load transient. The dynamic load recovers within 5µs with less than 0.8% peak-to-peak voltage, which minimises the effect on the static load side with a less than 0.1% peak-to-peak voltage. This circuit can be modified to accommodate other output combinations, like 0.8V and 1.8V, that can all directly supply the RFSoC load without the LDO regulator stage due to the ultralow noise in the low frequency range, low voltage ripple, and ultrafast transient response.
In time division duplex (TDD) mode, the noise critical LOs/VCOs become loaded and unloaded together with the transmit/receive mode changes. Thus, a simplified circuit as shown in Figure 3 can be used as all of the loads are considered to be dynamic load while a more critical postfiltering is required to maintain the low ripple/low noise feature for the LOs/VCOs.
A 3-terminal capacitor in feedthrough mode can be used to achieve enough post-filtering with a minimised equivalent L that maintains a fast bandwidth for the load transients. The feedthrough capacitor together with the remote side output capacitors forms two more LC filter stages while all the Ls come from ESLs of the 3-terminal capacitor, which is very small and less harmful to the load transient. Figure 3 also illustrates an easy remote sensing connection for the Silent Switcher 3 family.
Due to the unique reference generation and feedback technology, one only needs to Kelvin connect the SET pin capacitor’s (C1) ground and the OUTS pin to the desired remote feedback point. No level shifting circuits are needed for this connection. Figure 4 shows a 1A load transient response waveform with <5µs recovery time and <1mV output voltage ripple.
Figure 5: T8625SP with a pre-charge signal fed into OUTS pin to achieve fast transient response
Pre-charge Signals Drive Silent Switcher 3 Family for Fast Transient Response
In some cases, the signal processing unit is powerful with enough GPIOs, and the signal processing is well scheduled as the transient event can be known ahead of time. This usually happens in some FPGA power supply designs where the pre-charge signal can be generated to help power the supply transient response. Figure 5 shows a typical application circuit using the pre-charge signal generated
by the FPGA to provide a bias before the real load transition happens so that the LT8625SP can have extra time to accommodate the
load disturbance without too large of a VOUT deviation and recovery time.
The tuning circuit from FPGA’s GPIO to the input of the inverter has been omitted as the pre-charge signal is acting as a disturbance on the feedback. The level is controlled to be 35mV. Moreover, to avoid the pre-charge signal effect on the steady state, a high-pass
22 NOVEMBER 2023 | ELECTRONICS FOR ENGINEERS
filter is implemented between the pre-charge signal and the OUTS. Figure 6 shows a 1.7A to 4.2A load transient response waveform. The pre-charge signal is applied to the feedback (OUTS) ahead of the real load transient, whereas less than 5µs recovery time is achieved.
Active Drooping on Circuit for Ultrafast Recovery Transient
In beamformer applications, the
Figure 3: Typical application circuit for LT8625SP in dynamic/static combined RF loads]
Figure 4: Feed- through capacitor boosts transient response while maintaining mini- mised output volt- age ripple
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