Table 4. I2CCmd (12Bh) Register Format D15
D14 D13 D12
D11 0
lower than the high battery See tables 9, 10, and 11.
When ALRT is asserted from the MAX17330, the host will perform the following: Read Status register data If
Status.CA is set
Read ChgStat register
If ChgStat.Dropout = 1 ➔ increase VOUT If (ChgStat.CP or ChgStat.CT) =
1 ➔ decrease VOUT Clear
Status.CA
See tables 12 and 13. FProtStat Register
Optionally, once the device moves from the constant current (CC) phase to the constant voltage (CV) phase, the voltage generated from the step-down converter can be reduced as follows: •
If VBATT = ChargingVoltage Read ChgStat Register
If
ChgStat.CV = 1 ➔ decrease VOUT until VPCK = ChargingVoltage + 25mV
These are all the steps needed to manage a 1S2P charging configuration. Included in
MAX17330-usercode.zip is the Python code for configuring the buck converter (MAX20743) as well as the charger and fuel gauge (MAX17330). It also includes the Excel data log to capture important charging parameters and evaluate the step charging profile. By managing alert signals generated from the MAX17330, a microcontroller keeps the linear charger of the MAX17330 close to dropout, minimising power dissipation and therefore allowing high charging current. A battery pack using the MAX17330 stores the parameters for the installed battery that the host microcontroller needs to implement efficient fast charging. This allows OEMs to replace a standard charger IC device with a simpler and less expensive buck converter without compromising performance or reliability.
Conclusion
Device charging time is one of the most important user experience considerations. Using a buck converter like the MAX17330 makes it possible to efficiently manage a very high current to decrease charging time in a small IC package. The ability to support parallel charging with a very high current, such as with two MAX17330, enables developers to charge multiple batteries in a safe, reliable manner that keeps charging time to a minimum.
www.analog.com D7 dSOCen D6 TAlrtEn
D5 0
Table 8. Config (O0Bh) Register Format D15 0
D14 SS
D7 SHIP D6
D13 TS
D5 COMMSH FastADCen Table 9. FProtStat (0DAh) Register Format
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 X
Table 10. Status (000h) Register Format D15 D14 D13 D12 D11 D10 D9
D5 IsDis D4 X D3 D2 Hot D1 D0 Cold Warm
D4 1
D3 DRCfg D2 D1 CPMode D0 BlockDis
Table 5. I2 GoToSID
C ALRT Settings Alert High Primary/Secondary Address
0b00 0b01 0b10 0b11
ECh/96h 64h/1Eh E4h/9Eh 6Ch/16h
Table 6. nProtCfg (1D7h) Register Format D15
D14 ChgWDTEn nChgAutoCtrl D7 Reserved D6 PFEn D13 FullEn D5 D4 DeepShpEn OvrdEn
Table 7. Config2 (OABh) Register Format D15
POR_CMD
D14 0
D13 AtRtEn Alert Low Primary/Secondary Address
6Ch/16h ECh/96h 64h/1Eh E4h/9Eh
D10
D9
D8
D7
D6
D5
D4 GoToSID
D3
COVER STORY D2
D1 0 D0 IncSID
D12 SCTest D3 UVRdy
D11
D10
D9 CmOvrdEn ChgTestEn D2 FetPFEn D1 BlockDisCEn
D8 PrequalEn D0 DeepShp2En
D12 0
D11 0
D10 0
D9 0
D8 0
D12 VS
D4 ETHRM
D11 0
D3 FTHRM
D10 PBen
D9 DisBlockRead D2 Aen D1 CAen
D8 ChgAutoCtrl D0 PAen
D8
D7
D6
D5
D4 D3 D2 D1 D0 PA Smx Tmx Vmx CA Smn Tmn Vmn dSOCi Imx AllowChgB X Bst Imn POR x
Table 11. Config2 (0ABh) Register Format D15
POR_CMD D7
dSOCen
D14 0
D6 TAlrtEn D13
AtRtEn D5 0
D12 0
D4 1
Table 12. Status Register (000h) Format D15 D14 D13 D12 D11 D10 D9
PA
D11 0
D3 DRCfg
D10 0
D2
D9 0
D1 CPMode
D8 0
D0 BlockDis
D8
D7
D6
D5
D4 D3 D2 D1 D0 Smx Tmx Vmx CA Smn Tmn Vmn dSOCi lmx AllowChgB X Bst Imn POR X
Table 13. ChgStat (0A3h) Register Format D15
Dropout X X X X
D14 D13 D12 D11 D10 D9 X
X
D8 X
D7 X
D6
D5 X
D4 X
D3
D2
D1 CP CT CC FEBRUARY 2024 | ELECTRONICS FOR ENGINEERS
D0 CV
17
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