EMBEDDED TECHNOLOGY
Memory architecture for AI edge systems
As edge AI moves from experimentation to real-world deployment, memory bandwidth is becoming one of the most critical system bottlenecks. By Winbond
I
n many embedded AI inference applications, the processor itself is not the primary limitation—the memory interface is. Edge processors require signifi cantly higher bandwidth to handle growing AI workloads, yet they must still operate within tight constraints on power consumption, board space, thermal design and overall system cost.
Once the interface reaches its throughput limit, adding more compute capability delivers limited system-level gains. Expanding bandwidth through wider interfaces increases pin count, routing complexity and package size, while pushing higher data rates raises switching losses and thermal load— tradeoffs that are especially challenging in edge devices with limited design margins. Reducing the distance between memory and processor can improve transfer effi ciency, but conventional stacking approaches often introduce new challenges. Thermal dissipation becomes more diffi cult, routing density increases and performance constraints may simply shift rather than disappear under sustained AI workloads. This widening gap between AI compute demand and memory capability is where Winbond sees a key opportunity for its CUBE architecture.
CUBE enabling higher data throughput
CUBE (Customised Ultra-Bandwidth Elements) is an advanced memory architecture developed to provide a compact, effi cient and high-bandwidth solution for emerging edge AI applications. It is designed to meet growing data throughput demands without relying on the larger, more power-intensive memory approaches commonly used in data centre systems.
The architecture supports both Chip-on- Wafer (CoW) and Wafer-on-Wafer (WoW) front-end integration and is compatible with back-end 3D advanced packaging technologies, including Cap-interposer for
enhanced power delivery performance. Winbond is also working closely with foundries, OSATs and ASIC partners to build a broader ecosystem that supports next generation edge AI system integration. At the technical level, CUBE combines area-effi cient TSV design with advanced die-to-die interconnect technologies such as µbump and hybrid bonding, enabling higher I/O density, faster data transfer, and improved thermal effi ciency. It can deliver up to 256GB/s bandwidth per die, while a 4Hi stack can scale to 1TB/s, with energy effi ciency below 1pJ/bit. This makes CUBE well suited for edge devices requiring sustained AI performance within strict power and thermal limits.
CUBE also offers fl exible memory scaling, with densities ranging from one GB to two GB per die. A 4Hi confi guration provides four GB to eight GB total capacity, helping designers align memory resources with AI model size and workload requirements. Combined with model optimisation technologies such as TurboQuant, CUBE can help enable more advanced local AI processing directly on edge devices.
Its compact footprint is another important advantage. By stacking the compute die directly above the memory, CUBE reduces overall board space compared with conventional discrete designs, making it ideal for applications such as AR/VR devices,
38 JUNE 2026 | ELECTRONICS FOR ENGINEERS
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