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test procedure specific to their requirements. This test procedure may differ with regards to having wafer probe and automatic test equipment (ATE), or both, and may have different temperature insertions and with calibration over an extended measurement range.
In current times, as the shortage of commercial off-the-shelf chips continues, custom ASICs can also help deliver security of supply. The major differentiator, however, comes when an ASIC developer can offer all production test and software and hardware development in house. This is typically known as a full turnkey (FTK) offering.
Being able to develop a product unique to a customer’s needs is one thing, but having that nimbleness to make adaptations and improvements to the chip while it is in development, without needing to call upon external expertise, gives FTK ASIC developers the greatest edge over their non-FTK competition. And that agility and control over the final product translates into benefits for the end customer too. Because, by design, an ASIC is produced uniquely for the customer and their requirements, it must undergo a stringent test regime to ensure its performance matches agreed parameters. Opting for a FTK service means ASIC development and production test can be completed under one roof. In Swindon’s case, it is highly likely that the engineers designing an ASIC are situated just a few short metres away from the test facility, meaning real time support or additional oversight can be carried out with ease.
DESIGN FOR TEST The production test of today’s highly integrated ASICs is complex. A major advantage that an FTK ASIC company can deliver is by planning the test regime and coverage of the device during the design phase. This is commonly known as design
for test (DFT) where developing circuit design and test strategies occur concurrently. DFT is challenging for the engineers but the benefits far outweigh the frustrations.
The additional circuitry that may be required when incorporating DFT techniques, can marginally increase the amount of silicon required to implement the design. The savings however from enhanced testability will materialise in shortening test time, increasing yields and reducing early life field failures. And all these benefits result in a reduction in overall cost.
ATE AND WAFER PROBE
There are several elements that are paramount to a thorough ASIC test schedule. The first makes use of ATE, which refers to any apparatus that performs parametric tests on a device, known as the device under test (DUT), equipment under test (EUT) or unit under test (UUT). ATE systems are designed to minimise the amount of test time needed to verify that a particular device works, or to quickly find its faults, prior to the part being used in an end customer product. Expertise in the test of ASICs at this phase, where the identification of parts that do not meet specification, is crucial to the end customer. Delivering parts that are likely to fail in the field or at manufacture, will add cost to the customer. The alleviation of this potential is fundamental to the Swindon test department and to the design team.
Another core element of ASIC test is wafer probe. During this step, performed before a wafer is sent to die preparation, all individual integrated circuits that are present on the wafer are tested for functional defects by applying special test patterns to them. Test can either be conducted manually or
using ATE and is completed prior to the IC being sent to the die packaging phase. At Swindon, wafer probe test is carried out at multiple
temperatures - i.e. a hot, cold and ambient - to allow better test coverage and higher accuracy. This is particularly crucial when developing ASICs for tyre pressure monitoring systems (TPMS), where testing at multiple temperatures ensures a tight customer specification, that must adhere to stringent safety regulations, being met.
QUALITY GUARANTEED
During prototype verification tests, if the ASIC is not performing as expected, changes may need to occur. While making changes to the chip, known as respinning, may seem like a daunting, unwanted process, it is an occurrence that will avoid future test failures. Issues can arise when, for example, working with new nodes, and there is a learning curve for design teams to come to terms with the new node’s limitations and particular traits. That said, there are measures in place to ensure any changes are made smoothly and quickly. Production test can also identify anomalies.
Yield alerts on test systems can detect whether a yield drops below a certain level, alerting the operators to take action. Swindon’s real time yield analysis (RTYA) runs on all production cells, helping to identify any areas that require attention before they can turn into problematic issues. This can range from a wafer batch discrepancy or to a contact continuity fault within the ATE. Yield analysis is a constant factor for Swindon’s test engineering team and yield improvement initiatives are conducted at all times to maintain the quality of the product and provide sub one parts per million (PPM) field failure rates. As one of many continual improvements to the test process, Swindon has reduced the test time of DUT while increasing test coverage. This in turn minimises the final device cost but maximises performance through quality. The result is a dramatic increase in product repeatability, yield and overall test quality with a vast decrease in field failure PPM rates. Several elements go into production test to ensure a high yield and on time delivery of the final product. By opting for an ASIC supplier with an in-house production test facility, will ensure delivery of the highest quality of ASIC and an elevated level of service.
Swindon Silicon Systems
www.swindonsilicon.com
Instrumentation Monthly June 2023 43
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