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HPC 2017-18 | High-performance computing


and partners including HPC centres, research organisations and hardware manufacturers that can help to create a European exascale class supercomputer to rival competition in the US and Asia.


Te €20m investment over a 42-month


period is part of a total €50m investment made by the EC across the EuroEXA group of projects supporting research, innovation and action across applications, system soſtware, hardware, networking, storage, liquid cooling and data centre technologies. Funded under H2020-EU.1.2.2. FET Proactive


(FETHPC-2016-01) the consortium partners provide a range of key applications from across climate/weather, physics/energy and life science/ bioinformatics. Te project aims to develop an ARM Cortex technology processing system with Xilinx Ultrascale+ FPGA acceleration at Pflop level by approximately 2020. Tis could then lead to exascale procurement in 2022/23 and commercialised versions of the technology available around the same time. John Goodacre, professor of computer


architectures at the University of Manchester, said: ‘To deliver the demands of next generation computing and exascale HPC, it is not possible to simply optimise the components of the existing platform. In EuroEXA, we have taken a holistic approach to break-down the inefficiencies of the historic abstractions and bring significant innovation and co-design across the entire computing stack.’ Peter Hopton, founder of Iceotope and


dissemination lead for EuroEXA, said: ‘Tis is a world-class programme that aims to increase EU computing capabilities by 100 times, the EuroEXA project is truly an exceptional collection of EU engineering excellence in this field.’ Te EuroEXA project is certainly ambitious


as it hopes to bring technologies from ARM and Xilinx together with Maxeler and memory technology from ZeroPoint Technologies to produce a new computing architecture for an exascale system. Even if this process is successful, it will


require a lot of application development to create the tools necessary to deliver sustained exascale performance. Alongside the scalable vector extensions (SVE) Arm has helped to provide Allinea debugging tools and the project has partnered with several research centres that bring their own large-scale application codes for development. Arm is providing Allinea tools as a bridge


between the hardware architecture and applications, evaluating application performance and pinpointing steps to maximise efficiency. Te tool selection for the EuroEXA Program


16


enables Arm to collaborate with project partners and understand their challenges in application development and preparation on the novel EuroEXA platform. ‘New capabilities are oſten a direct result of collaborating with leading research efforts such as EuroEXA. Arm is quickly applying learnings from EuroEXA, and similar efforts, into future state-of-the art Allinea tools designed to help reach the most efficient levels of exascale compute,’ said David Lecomber, Arm’s senior director of HPC tools. Another project partner, Maxeler, hopes


to port its Dataflow programming model to support the relevant components of the EuroEXA platform. Ultimately, this should allow the applications targeted to be brought on to the heterogeneous EuroEXA system platform.


Technology, Goteborg, Sweden. Te firm has developed memory systems that use an IP- block that compresses and decompresses data in memory, so that typically three times more data can be stored in memory and transferred in each memory request. Teir aim is to deliver added value and competitiveness concerning cost, power consumption and performance of exascale systems, plus added value in power consumption and memory performance by adapting its intellectual property blocks and integrating them in the computing chips. Additionally, the company will be responsible for the memory interface for the EuroEXA project. Per Stenstrom, co-founder and chief scientist


from ZeroPoint Technologies, said: ‘We are very excited at having the opportunity to join the EuroEXA project and demonstrate the added values our unique technology can offer to Exa- Scale systems.’ Iceotope will also be aiming to provide a


boost to power consumption and efficiency with its liquid cooling technology, which should allow denser computing racks and more efficient cooling technology. However, the company was not just selected for its capabilities in liquid cooling, but also for IP within power delivery, I/O connections, infrastructure management and data centre infrastructure. Peter Hopton, founder of Iceotope said: ‘It’s a


In EuroEXA, we have taken a holistic approach to break down the inefficiencies of the historic abstractions and bring significant innovation and co-design across the entire computing stack


‘Joining EuroEXA is exciting for us because it


allows us to bring our long-established Dataflow technology into Europe’s latest effort towards achieving Exascale performance,’ said Georgi Gaydadjiev, director of Maxeler Research Labs. Te Dataflow computing model will enable


application developers to utilise the reconfigurable accelerators in a high-level environment. It also addresses the practical challenges of data movement when combined with other technologies, such as memory. Memory specialist ZeroPoint Technologies


uses novel compression approaches to store and transfer memory data more efficiently. Te technology is based on more than 15 years of research from Chalmers University of


privilege to be selected as part of this programme, with this investment in development, our technology will now enable the biggest computers of the future, as well as the cloud computing environments and edge computing of today and the near future.’


Leaving a legacy Creating an exascale supercomputer is a huge achievement, but if the accompanying soſtware stack, programming models and even core design do not see widespread use by the wider HPC community, then all the effort that has been exerted will be lost in the transition to following generations. While one measure of success is the system


capable of a huge number of calculations, it is clear that there is an opportunity to develop better standards and approaches to computing that can provide benefits over the next five to 10 years. One example of the negative side effects


that have come from several generations of computational evolution along the von-Neumann architecture is the memory bandwidth bottleneck that we see in today’s most computationally intensive HPC systems. Te problem is not just confined to the


performance from a lack of data transfer, as the energy ratio between control and arithmetic I/O


Style-photography/Shutterstock.com


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