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high-performance computing


Accelerating the development of HPC


Robert Roe investigates how accelerators are


driving the design of new architectures in HPC to solve the challenges of exascale computing


S


ince their introduction to HPC, accelerators have seen increasing success as more people have developed the knowledge and skills to


use them and programmers have adapted their previously serial code to run more efficiently in parallel. Two of the three next-generation US


national laboratory supercomputers, funded through the US Department of Energy (DOE), will make use of Nvidia GPUs tightly integrated within the IBM Power architecture. In addition, the DOE’s FastForward2


project, funded in conjunction with the US National Nuclear Security Administration (NNSA), aims to develop extreme scale supercomputer technology still further. Te project awarded $100 million in contracts to five US companies which included Nvidia, AMD, and Intel. Tese programmes, and similar projects


in Europe, demonstrate that accelerators are a critical tool for HPC as it approaches the exascale era. Parallelising code and running it on power-efficient accelerators has become a necessity, if we are to reach the ambitious power consumption targets set out by the US and European governments. Roy Kim, group product manager in


Nvidia’s Tesla HPC business unit, stated: ‘It’s an interesting time right now for HPC. A few years ago, Nvidia GPUs were the only accelerators on the market and a lot of customers were getting used to how to think about and how to program GPUs. Now if you talk to most industry experts, they pretty much believe that the path to the future of HPC,


38 SCIENTIFIC COMPUTING WORLD


The internal processor Die of the Intel Xeon Phi coprocessor product family, manufactured using 3D Tri-gate 22nm transistors


the path to exascale, will be using accelerator technology.’


An ecosystem, not just a GPU A large part of the success of GPUs has revolved around Nvidia and its ability to generate a large skill-base around its GPU programming language, Cuda. Not only did it have a head start due to its dominant position in the consumer GPU market, but it also invested heavily in higher education. Tis enabled the development of academic programmes such as the Cuda centres of excellence, in addition to GPU centres and other activities to increase adoption of the technology. Te end result of all this activity is that


Nvidia managed to generate a soſtware ecosystem based around students and computer scientists who understand Cuda and how to make the best use of Nvidia GPUs, which helped to spur technology adoption. Kim said: ‘Te higher education community really fuels the rest of the industry. Whether it’s


HPC or enterprise computing, the next wave of developers comes from higher education and we recognise that. We have these academic programmes as well as a lot of resources invested, to ensure that parallel programming is taught on GPUs.’ Kim stressed that a lot of the success that


Cuda has had is because it made parallel programming easier, so that developers were


THE PATH TO


EXASCALE WILL BE USING ACCELERATOR TECHNOLOGY


able to spend time optimising applications or creating new code rather than having to grasp the concepts with parallel programming. However, Nvidia is not the only horse in the


race today, as companies like AMD and Intel set their sights firmly on the server and HPC markets.


@scwmagazine l www.scientific-computing.com


Intel


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