M a g a z i n e o n 3 d - i C , t s v , W l P & e m b e d d e d t e c h n o l o g i e s I S S U E n ° 1 7
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What is the impact of Xilinx’s 3D silicon interposer announcement?
Xilinx made a big announcement last month when announcing their intention to commercialize 3D silicon interposers based on TSV interconnects for their next- generation 28nm FPGAs in their Virtex 7 future product line.
Let’s look at why this announcement is so important: To begin with, Xilinx is the first large semiconductor company to jump into the free space of 3D integration in the logic area. It’s quite impressive that a fabless company is taking the first big step in this new direction for manufacturing. Indeed, Xilinx is kind of “cleaning the pipeline” so that other players can quickly follow in the FPGA and high-performance ASIC spaces.
To be continued on page 2 a N a l Y s i s
The wide I/O interface is already being embraced as the next step in the evolution of 3D IC integration. Next up for 3D ICs: Wide I/O
For starters, South Korean-based electronics giant Samsung hails the wide I/O and through-silicon via (TSV) combination as the “best of both worlds” in terms of achieving performance and thin multiple- die stacks.
Memory maker Elpida, based in Tokyo, Japan, is actively developing next-gen mobile wide I/O DRAM, which expands the I/O interface bus width, and mounting technologies that use TSVs. In fact, Elpida has installed a production line at its Hiroshima Plant to develop TSV and mass production technologies for multiple connections using TSVs.
And Nokia, an Espoo, Finland-based leader in the transformation and growth of the converging Internet and communications industries, describes the evolution of 3D IC integration as moving from 2.5 to true 3D, relying on various applications of TSVs in silicon interposers, memories, and ICs. The company plans to integrate wide I/O interface structures using TSVs for mobile phones in volume by 2013.
any companies are publicly discussing their 3D IC integration roadmaps and the role wide input/output (I/O) interfaces will play.
Why I/O interfaces?
When asked what’s fueling the drive to use wide I/O interfaces for 3D ICs, answers vary slightly from company to company but a theme is clearly emerging.
As handheld devices become increasingly more sophisticated, applications are emerging that require much higher memory bandwidth, says Jeff Brighton, director of CMOS 3DIC technology development at Texas Instruments (TI; Dallas, Texas). “However, fundamental power and thermal limitations remain the same as in today’s handsets. The initial version of a wide I/O memory interface will deliver 12.8GB/s of memory bandwidth—while keeping the processor plus memory system-on- chip (SoC) power consumption under control,” he adds. ...
Wide I/O interface with TSV for Mobile processors (Courtesy of Texas Instruments)
C o M P a N Y v i s i o N Interview with Dr. William Chen of ASE
Yole Développement recently had an opportunity to interview William (Bill) Chen about his long career in microelectronics packaging and his current activities as a part of ASE.
Yole Développement: Dr Chen before we start our questions on ASE, can you share a little on your past history. It’s our understanding that you had a full career at IBM before coming to ASE and that you just finished two terms as President of the IEEE Component, Packaging and Manufacturing Technology Society (CPMT). Can you fill us in on this part of your past?
Bill Chen: After I completed my PhD studies at Cornell University, I started working at the IBM Development Laboratory in Endicott New York. It was still at an early point in the history of electronics and certainly an exciting time at IBM. I soon gravitated to work in electronic packaging. The science was intriguing and technology was
new. I learned how to do engineering from concept nucleation, feasibility demonstration, and product development to manufacturing. I spent over 33 years at IBM in various technical and R&D management positions. After retirement, I joined the Institute of Materials Research and Engineering (IMRE) in Singapore. My initial role at IMRE was to establish a research program in Electronic Packaging within this young Research Institute. As it turned out I became the Director of IMRE, nurturing the young Institute to become the premier materials research institute in the region. I retired from IMRE to join ASE in 2000. I was President of IEEE CPMT Society from 2006 to 2009.
I am currently co-chair of the ITRS Assembly
and Packaging ITWG. I have been elected a Fellow of ASME and IEEE.
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C o M P a N Y v i s i o N s 6 a N a l Y s t C o r N e r
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