A UGU ST 2010 issue n°16 Newsletter on 3 D I C, T S V , W L P & E mbedded Technologies
A N AL Y ST C OR N ER Why the secrecy surrounding TSI development?
Yole Développement analyst Jean-Marc Yannou describes what’s really going on behind the scenes with through-silicon interposer (TSI) development.
t seemed like the industry had shifted to an age of collaboration, away from secrecy. But this just isn’t the case with TSI development.
As Yannou puts it: It’s difficult to get people to discuss advanced subjects and, in particular, this one.
device remain essentially forward-looking
or silent on the topic, occasionally publishing
featuring the advantages or challenges associated with 3D silicon/ glass interposers.
and packaging service (OSATs) and foundries
aren’t really publicly discussing TSIs, aside from presenting marketing roadmaps to show that they’re “ready”—without investment
manufacturers of any capacity organic
Phil Garrou, Senior Analyst,
substrates are all looking into TSIs, because the technology is being eyed as a next-gen substrate for some applications. They’d like to get a jump on this and control it, since their primary focus is to sell organic PCBs and it would be nice to keep that business rolling as long as possible. Some small companies and others that aren’t heavily involved in the semiconductor
but rather are involved in MEMS, are proposing technology solutions and willing to speak somewhat publicly about
outside the semiconductor
MEMS packaging and even mechanical glass assembly players, are proposing using 3D glass
their efforts. Surprisingly, many industry, especially
Advanced Packaging, Yole Développement
Jean-Marc Yannou, Project Manager, Advanced Packaging, WLP & 3D system Integration,
Yole Développement interposers and claiming that they
can do it at a much lower cost than anything using silicon.
So why don’t companies want to talk about their plans for TSIs? There are several plausible explanations why companies are keeping quiet.
“The benefits of TSIs aren’t proven across all applications,” Yannou says. “Their drivers may differ quite a bit between various applications, and cost for
remains a many—even serious though
performance benefits are expected. For this reason, companies might not want to risk announcing investments for TSI, even though it seems necessary to achieve cost competitiveness.”
Another is that the technology “entry barrier” to TSIs isn’t high and many companies are able to develop it. As a result, he notes that there is little interest or
in industry less interest than for other
of technology under development. Collaboration is now generalized to CMOS developments, and technology
differentiation is increasingly expected from packaging, assembly, and mid-end technologies such as TSIs.
Because these are relatively simple technologies when compared to CMOS,
the question isn’t
how to make TSIs; it’s how to use them. The answer is very far from obvious, Yannou believes, because many things need to be considered before making choices. This
any system-in-package (SiP) includes: expected electrical and
thermal benefits, miniaturization, reliability, cost, alternative technologies, capital investment, and available infrastructure. This can all lead to secrecy surrounding TSIs.
“For applications such as MEMS, CMOS image sensors, logic and memory 3D integration, it isn’t yet clear if TSIs will be a long-lasting trend or just a bridge technology waiting for true 3D ICs, much like TSVs in CMOS, to replace them,” says Yannou.
What would happen if the industry decided to collaborate? Yannou thinks it would likely spur the needed investments and the adoption of TSIs. “There are already some R&D collaborations between fabless
companies and foundries or
OSATs or memory companies. They are trying to identify together the opportunities and challenges of TSIs for applications like GPUs and FPGAs,” he adds.
At the moment, the biggest question surrounding TSI development is: Will it be a big high-volume deal, a niche technology, or one that is avoided altogether? Yannou doubts it will be a big hit across all envisioned applications, but there will be some applications for it. It’s already being used in CMOS image sensors and MEMS wafer-level capping.
And another question on many people’s minds: If TSIs are a bridging technology, waiting for full 3D
“Technology differentiation is increasingly expected from packaging, assembly, and mid-end technologies such as TSIs” explains Jean-Marc Yannou, Yole Développement.
3D Interposers can solve the reliability issue of low-K dielectrics
for high IO density circuits (Source: Yole Développement - 2010)
ICs, how long will the technology be used in high- volume production? And this is quite difficult to predict, he says, but it could range anywhere from three to 10 years.
That brings us to cost. Cost is, of course, always a huge issue. No exception here.
compute the target cost for a silicon interposer, you need to do it at the complete system level or at least die/package level to find the intrinsic cost of the interposer itself,” Yannou says.
Interested in a universal cost metric for a TSI? According to Yole’s cost simulations, it’s going to need to cost about 1 cent/mm2 or less for a TSI, otherwise it doesn’t stand a chance of becoming
(Courtesy of Yole Développement, 3D Glass & Silicon Interposers – 2010 Report) 14
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