F E B R U A R Y 2 0 1 0 i s s u e n ° 1 4
N e w s l e t t e r o n 3 D I C , T S V , W L P & E m b e d d e d T e c h n o l o g i e s
devices, but there are still some issues. We need NMD: What about lowering production costs? NMD: Is customer attitude changing towards
to bring down the interposer costs, improve the TA: The cost of making TSVs is currently around TSV chip stacking?
high reliability test technology, and reduce process $130 to $150 per wafer. The target is often said to be TA: We are currently talking to customers who are
costs. On the stacked DRAM chips we will ship in $100. This level appears to be within reach, but we looking for higher performance for graphics and
2010, the TSV position on all the chips is the same, would prefer it to be lower still. Our internal goal is server management applications. I used to get the
so no interposer is needed. But to stack different $50. But getting there will require a radical change impression that customers were looking far ahead,
kinds of chips, interposers will be required. To stack in production technology. The particular bottleneck but lately they’re starting to talk about nearer time
a logic chip that tends to have the TSVs in the center is etching the vias and filling them with copper. We frames.
with a memory chip that has them on the periphery, are re-thinking these steps.
for example, we’ll have to use an interposer layer to
connect the circuits. NMD: What about attaching the chips?
TA: Currently we are using solder bumping. In the Paula Doe for Yole Développement
NMD: How will interposer costs be reduced? future direct copper-to-copper metal bonding will Translated by permission of Nikkei Microdevices
TA: Hard issues still remain. Silicon has excellent likely be necessary, so we are developing that.
heat expansion and electrical properties, but it is One key is the technology for cleaning the bonding
Takao Adachi, Elpida Memory,
too expensive to use. Resin is a possibility, but surface. We are developing a special liquid coating,
Director and CTO, New
there is not yet a specific strong candidate. but it is not yet ready for commercial production. I Technology Development
think stacking the chips after dicing (chip-to- chip)
NMD: How about the other issues? will be the main approach. Wafer-level stacking
Elpida Director and CTO Takao
TA: For the DRAMS we are shipping in 2010, we use before dicing (wafer-to-wafer) is possible, but
Adachi previously served as the
dedicated test circuits on the chips, but these waste won’t work for chips of different sizes, and will also
general manager of technology
development. Prior to joining Elpida, he was
chip real estate, so we aim to eliminate them. But have issues with lower yields. But a wafer-scale
project manager of planning and development
this will require probing several thousand fine pitch process could be used to put each chip on a silicon
for the First Memory Division of NEC. He also
elements per chip without static electricity damaging interposer. concurrently serves as a director of Rexchip
the circuits. It’s an extremely difficult business and
Electronics Corp. in Taiwan. (Courtesy of Nikkei
we haven’t yet perfected the technology.
Microdevices)
TSV CoSim +
TsV Manufacturing Cost simulation Tool
Evaluate the Cost of Ownership for your TSV Scenario with this New Version
of Yole Simulation Tool
KEY FEATURES
T he functions:
• Possibility to run the cost simulation for different geographical zone,
clean room class …
• Integrated fab units database
• Integrated Alchimer AquiVia process for comparison between
wet and dry processes for insulation/seed/barrier
• Integrated equipment, wafer & materials databases
• Two calculation modes: dedicated and non-dedicated fab
• Up to five scenarios simulation allowing the user to compare
yields improvement, manufacturing location impact on cost…
The use of TSV CoSim+ :
Y O L E D É V E L O P P E M E N T
• Understanding of the cost structure
• Competitive analysis
• Cost evaluation for different technological options
• Identification of the cost pain points in your process
Y O L E D É V E L O P P E M E N T
ConTACT Us
For more information, feel free to contact David Jourdan,
Y O L E D É V E L O P P E M E N T
Tel: +33 472 83 01 90, Email: jourdan@yole.fr
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