Show preview: Productronica 2009
New thermal measurement tool to help manage increasing thermal loads
Joe Fjelstad
New thermal measurement tool to help
manage increasing thermal loads
Heat is a significant byproduct when ability to meet thermal requirements, 2) parallel, cover 87% of the die surface to
almost any electronic product is operated. Thermal simulation and verification of provide uniform heating to each half of the
In a perfect world, there would be no resis- package capability, 3) Evaluating package cell, as needed.
tance in circuits or in circuit elements, and mechanical response to stress generated by The thermal test chip itself has
no matter how fast one turned on and off internal thermal testing loads, 4) Mapping two fundamental application-oriented
the millions or billions of transistors in an of thermal effects, both local and global, attributes. First, the device has the ability to
electronic product or system, there would and 5) Both board and system level thermal generate heat flux by the power dissipation
be no (or little) excess energy to account for simulation. in the heating resistors, and second, it has
and manage. Unfortunately, that is not the ability to measure temperature by taking
world we live in, and managing that excess advantage of the temperature-dependent
energy is an increasingly important task for nature of diode forward voltage. Both of
the electronic product designer. One of the these attributes are essential to the chip’s
challenges facing the designer is accurately target applications, specifically thermal
characterizing the product to understand measurement of semiconductor packages
the thermal challenge and assure that an and thermal simulation of semiconductor
adequate solution is provided for in the fi- devices.
nal design. While finite element modeling While thermal test chips have been
of an electronic product is very useful and widely used to help mitigate or eliminate
important, there is nothing like empirical electronics heat dissipation problems
experimentation and results to provide the from package to system level, provide
kind of data that the practical line engineer thermal characterization, facilitate package
likes to see and work with before sending assembly process optimization and improve
the product out into the world. heat sink thermal solution evaluation,
To help address this need, a new
 
they have also proved of value when
solution has been recently introduced
Figure 1. Layout and electrical structure of the test
semiconductor manufacturers do final
by Thermal Engineering Associates, Inc. chip cell. test on packaged semiconductor devices.
(www.thermengr.com) in Santa Clara, Often they have to make parametric and
Calif., in the form of a new thermal test functional measurements over an extended
chip. The new chip complies with the The new test chip is based upon a temperature range such as 0˚C to +70˚C
EIA/JESD51-4 standard
1
titled “Thermal novel unit cell design (Figure 1) that is 2.5 for consumer electronics or -25˚C to
Test Chip Guidelines” and, according mm on a side and repeated to form up to +85˚C for commercial parts. However,
to the developers, is flexible enough to a 40x40 matrix. This allows the user to while these temperature ranges refer to
meet virtually all of the requirements for activate one cell individually or combine the junction temperature, most of the
general purpose semiconductor thermal and activate as many cells as needed, up time the manufacturers have no way to
testing applications. For the reader’s to the limits of the matrix. Regardless actually make this measurement. Thus
reference or recall, thermal test chips are of the number of cells chosen, periphery by putting a thermal test chip into the
specially fabricated semiconductor devices connections provide access for all heating same package as they are trying to test,
capable of delivering precise thermal and Kelvin enabled measurement need. manufacturers have a way to monitor the
flux sources in specific geographic areas In use, strategically placed diode sensors junction temperature when the device,
of a semiconductor package or printed enable temperature measurements after being subjected to preconditioning, is
circuit board in order to simulate the in the center, center periphery and inserted into the test site. This is important
thermal performance characteristics of opposite diagonals, regardless of the size because leakage tends to double with every
the subsystem. Traditional applications or configuration of the cell array. Two 10˚C increase in junction temperature;
for thermal test chips have included: 1) individual metal film heating elements, thus if the manufacturer thinks the
Evaluation of new or current IC package which may be connected in series or in junction temperature is at a certain point,
50 – Global SMT & Packaging – October 2009 www.globalsmt.net
Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44  |  Page 45  |  Page 46  |  Page 47  |  Page 48  |  Page 49  |  Page 50  |  Page 51  |  Page 52  |  Page 53  |  Page 54  |  Page 55  |  Page 56