Title
IC packaging technology retrospective—part 6
Joe Fjelstad
IC packaging technology
retrospective—part 6
Packaging solutions enter the third dimension
Though chip packaging was reduced to weight and volume requirements of world where there is ever greater interest in
true chip size using WLP as was discussed more demanding military and aerospace stacking of chips within a package to create
in part 5 of this series, it did not mark the applications. More recently Vertical what some have called system in package
end of the road for IC package innovation. Circuits has been developing advanced (SiP), stacking packages on packages (PoP)
Product developers eager to put more solutions along the same lines but with and placing packages within packages
function into the same footprint hit their own special processing methods. (PiP) to improve functional density while
upon the idea of stacking both chips and While these methods are effective, the addressing the challenge of yield and even
packages and went after this seemingly new structures are monolithic and have putting packages under packages (PuP).
dimension with a great deal of vigor. The required assembly equipment and methods Chip stacking is now in fairly wide use
phrase “seemingly new” was used because that are not in broad use. One of the by both semiconductor manufacturers and
the roots of the stacking concept go back challenges that is shared by any who chose subcontract assemblers. Although the die
more than two decades to the development to go this path is assuring that all the die used are typically memory combinations
of “memory bricks” for military products that go into the assembly are of impeccable such as flash memory and SRAM, more
in the 1980s. Companies such as Irvine quality to in turn assure that overall quality complex stacks with up to nine die
Sensors, DensePac, and Stacktek developed an reliability of the final assembly will meet assembled of various types are being
volumetric packaging solutions for memory expectations and requirements. fabricated and shipped some in appreciable
chips to meet the need for greater amounts Since chip-scale packaging has been volume. Figure 1 provides an SEM
of memory in advance of the pace afforded widely embraced by the memory industry micrograph of one such structure.
by Moore’s Law and to meet stringent and by computer designers, who are always The issues that limit chip stacking
hungry for ever increasing solutions are the same ones that were faced
quantities of memory, the by MCMs: compound yield concerns,
notion of stacking finished assembly complexity, sourcing KGD and
memory packages was managing multiple die vendors. One
also widely embraced and solution to this nagging problem has been
again this is not that new. to stack not just die in packages but also
Stacking of DIP packages packages on packages (PoP). Amkor, Stats-
on memory cards has been ChipPac, Tessera and others have taken
going on for some time. on the challenge and an extreme example
Regular readers may recall from the latter can be seen in Figure 2.
the Small Matters column In addition to the 3D solutions of
written a few years ago where stacking of chips and packages and the
there was described a project embedment and stacking of packages
in which this writer was within packages, there has been interest
involved nearly 25 years ago. in folding packages to accomplish certain
!
It had chips on two sides design objectives. These are also not all
of a common package, and that new, folded IC package assemblies
Figure 1 Stacked chip packages can help significantly conserve PCB
that package had mounted were a packaging solution that have been
real estate and with the use of thinned die, very little penalty in the Z
upon it another package. used successfully for medical applications
axis; however, die yields must be near perfect. Such structures are com-
monly employed to create system in package (SiP) alternative solutions
The final assembly was then and specifically in hearing aid designs since
to the time and expense of designing a complex and expensive chip.
surface mounted. That aside, at least the 1980s but they have recently
we now find ourselves in a
44 – Global SMT & Packaging – August 2009 www.globalsmt.net
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