IC packaging technology retrospective—part 5
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Figure 2. Wafer level packaging taken to the extreme could redefine the relationship between the IC and package
as inferred in the image above.
basic process steps and an example of one considered for with each inevitable die
of these early devices. Other companies shrink, the package footprint will typically
picked up on the general concept of wafer change, the result of which is that the next
level packaging, and a range of creative level interconnection substrate such as a
solutions were introduced. ShellCase in PCB could require a redesign with each die
Israel (now part of Tessera) came up with shrink. Even so, the wafer level concept has
a solution that was nearly identical to the remained attractive due to it ability to par-
M-Pulse process several years later, and allel process and test and it is being used
that process is now being successfully used for an ever-increasing number of chips.
for miniature cameras for cell phones and In the next part of this retrospective,
other applications. we will look back at origins of three-dimen-
Most other wafer level packaging sional packaging.
solutions have been variations on the
wafer level redistribution of I/O concepts
developed at IBM, but some solutions were Verdant Electronics founder and president
quite unique. Form Factor, for example Joseph (Joe) Fjelstad has more than 35 years of
developed a novel formed-and-plated gold international experience in electronic intercon-
wire process that, while not cost effec- nection and packaging technology in a variety
tive for wafer level, proved successful for of capacities from chemist to process engineer
wafer testing. Tessera was also an early and from international consultant to CEO. Mr.
proponent, innovator and developer of Fjelstad is also a well known author writing on
feeds.feedburner.com/
wafer level packaging concepts. Most of the subject of electronic interconnection technol-
globalsmt/VOaE
their solutions were centered around their ogies. Prior to founding Verdant, Mr. Fjelstad
basic concept of a chip scale package that co-founded SiliconPipe a leader in the develop-
provided strain relief to obviate the need ment of high speed interconnection technologies.
for underfill, a method that is required for He was also formerly with Tessera Technologies,
most other wafer level packages beyond a global leader in chip-scale packaging, where he
the smallest to protect the delicate solder was appointed to the first corporate fellowship
joints. Exploration of ideas around the for his innovations.
general concept lead to some interesting
prospective solutions, including one some-
what radical concept that suggested the use
of the package to share functions with the
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IC and accommodate power, ground and
mobile device
cross-chip interconnections (Figure 2).
While wafer level packaging remains
attractive and is seeing broader use in a
greater range of applications, there are
concerns of cost and yield that users have
found which require address. The reality
is that for wafer level packaging to be truly
cost effective, the package yield must be
near the same to the wafer chip yield. Die
shrink is another concern that must be
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www.globalsmt.net Global SMT & Packaging – June 2009 – 37
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