Title
IC packaging technology retrospective—part 5
Joe Fjelstad
IC packaging technology
retrospective—part 5
The emergence of wafer level packaging
Semiconductor packaging technology has technologist to apply the technology to its used on ceramic interconnection substrates
followed a circuitous path forwards and now widely known C4 (controlled collapse that were extremely planar and had a
backwards in time over the course of its chip connection) assembly process. As I/O relatively good CTE match to silicon. (7
evolution. Early structures and methods of counts increased in the early 1960s, IBM’s ppm/˚C versus 3 ppm/˚C). Unfortunately
interconnection and packaging described forward-thinking packaging technologists the rest of the industry was using organic
in earlier parts of this series were simple developed a process for redistributing the substrates, which had a nearly six times dif-
as the devices themselves. The reader will I/O to an array that was more convenient ferential in terms of expansion rates (18-20
recall from part one that some of the very for designing and making next level inter- ppm/˚C versus 3 ppm/˚C). Bare silicon
first packages for transistors were created connections. This early back end of line chips were, at that time, not viable except
on the wafer. The wafers of that time were (BEOL) process seems to nicely mark the for very small, few I/O devices. Still there
very small by today’s standards (25 mm to origins of what is now commonly called the was desire for smaller packages. Chip scale
50 mm then versus 200 mm to 300 mm wafer level process today. packages offered the benefits of flip chip
today). With only three I/O per device, The flip chip process was limited to with the benefits of packages. It did not
it was a simple and seemingly logical ap- IBM and a few of its licensed suppliers for take long for visionaries to see the possibil-
proach. Arguably, the most well known of many years and was not well appreciated as ity of creating the package on the wafer and
these early “package” structures were the most of the rest of the industry was focused the performance increase and cost reduc-
flip mounted transistor chips that IBM on wire bonding for chip interconnection. tion potentials it offered by performing all
used in the manufacture of the modules Wire bonding had established itself as of packaging activity en masse.
used in their ground breaking IBM 360 reliable and easily adapted to new products The term “wafer-level packaging”
computer. These tiny devices likely served with simple adjustments. Moreover the (WLP) entered the industry’s lexicon
as the inspiration for the company’s flip chip technology developed by IBM was in the late 1990s. In general wafer level
packaging is technology wherein the die
interconnects are manufactured and tested
on the wafer and sub sequentially diced
into discrete packages for assembly in a
surface mount line. Initially, the process
was reserved largely for small die because
the thermal mismatch between the silicon
which generally dominated the package
and the printed circuit board substrate to
which it is mounted is less problematic due
to the smaller dimensions; however, this
has changed with solutions which mitigate
the stress and strain associated with the
mismatch.
One of the first companies to develop
a process for packaging the IC while they
were still on the wafer was M-Pulse (later
!
Chip Scale, Inc.). Their engineers cre-
Figure 1. Basic process steps for the µSMT package one of the earliest true wafer level packages.
ated peripherally leaded packaged devices
on the wafer in 1990. Figure 1 shows the
36 – Global SMT & Packaging – June 2009 www.globalsmt.net
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