Cost reduction of wafer level packaging by using established materials from non-electronics industries
paint is applied, about 15 µm thick. com/technologies/products/wafer_level_ Conference, held in San Jose, California,
csp/shellrt.htm October 13-16, 2008. IWLPC is sponsored
reliability 5. Powercron 645 manufactured by PPG jointly by the Surface Mount Technol-
Components intended for integration into (UK) Ltd. ogy Association and Chip Scale Review
products must be fit for purpose. Meeting 6. G. Humpston, L Mirkarimi, and M. magazine
this criterion is usually demonstrated by Huynh, “Board Level Reliability of
subjecting batches of components parts Solid State Camera Modules”, Pro- Giles Humpston received his BSc in metallurgy
to various environmental regimes, which ceedings IMAPS 40th International and his PhD in alloy phase equilibria from
must be survived. For conventional semi- Symposium on Microelectronics, San Brunel U., England. He is director, research
conductor parts, these tests are defined Jose, 13-14 November 2007 and development, at Tessera, 3099 Orchard
by Standards, one of the more arduous of Dr., San Jose, CA 95134; ph 408/123-4567,
which is for automotive applications. The acknowledgements e-mail
ghumpston@tessera.com.
principal package- and board-level tests and This article was presented as a paper at
accompanying environmental parameters the International Wafer-Level Packaging
are summarized in Tables 1 and 2.
A typical test sample comprises a
minimum of three lots of 77 parts taken
from production batches manufactured on
different days by different shifts on the full
range of equipment available. SHELL-
CASE® MVP parts exhibit a margin of
safety of more than two and often substan-
tially more
6
over the required reliability
Standards.
conclusions
Packaging of solid state imagers is prefer-
ably accomplished at the wafer level since
this approach is compatible with surface
mount assembly and provides for a more
compact, more reliable and lower cost
solution than COB assembly. Protection
of the front face of the imager is provided
by a cover glass. This part obscures the
bond pads on the die necessitating contact
to be made either at the edges of the die
or through its thickness. Because through
silicon vias are not yet a commercial
reality, an alternative approach based on
via-through-pad interconnects has been de-
veloped. This is a low cost solution because
it is based on extremely cheap polymers
developed for the automotive industry and
readily available equipment set. There are
few restrictions on the bond pad size, pitch
or location, making it directly compatible
with the majority of existing CMOS imag-
ers. The packaged imager is able meet and
surpasses both cell phone and automotive
reliability standards for components and
board level systems.
references
1. A. Chowdhury, “Camera Module As-
sembly and Test Challenges”, Semicon-
ductor International, February, 2006
2. Prismark Partners LLC, November
2007
3. F. Laermer and A. Schilp, “Method of
Anisotropically Etching Silicon”, US
patent No. 5,501,893, 1996
4. Tessera, Inc., “SHELLCASE® RT”,
December 2006. http://www.tessera.
www.globalsmt.net
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