Cost reduction of wafer level packaging by using established materials from non-electronics industries
Test and Standard Conditions and Duration
that thickness, the film insulates the part
so attraction stops and electrocoating is
Preconditioning – moisture soak level one 125 +5/-0 ºC, 24hrs
complete. The thickness is controlled by
(MSL1) 85 +/-20 ºC; 85 +/-5% RH, 168hrs
the voltage applied to the electrocoat bath
Gradient <30 ºC/sec
and typically ranges from 5-75 µm. Electro-
100-150 ºC for 60-120sec
phoretic paints were developed to improve
183 ºC for 60-150 sec
the corrosion resistance of car bodies with
265 +0/ -5 ºC for 10-30 sec
added benefit of excellent colour and gloss
Gradient <6 ºC/sec
control compared with sprayed paints.
Time from 25 ºC to peak <8 min
They do not contain heavy metals, gener-
x 3 cycles
ate little or no hazardous air pollutants and
Temperature and humidity after MSL 1 85 +5/-0 ºC
liberate very low levels of volatile organic
JESD22-A101-B 85 +/-2 ºC; 60 +/-3% RH
chemicals. Bake temperatures are typically
2000 hrs
around 120ºC. Above all, they are very low
High temperature storage after MSL 1 150 +/-5 ºC cost and some grades of electrophoretic
JESD22-A103-A 2000 hrs paint can endow steel parts with corrosion
Thermal cycling after MSL 1 Min: -40 +0/-10 ºC ; Max: 125 +15/-0 ºC
resistance in excess of two thousand salt
JESD22-A104-B 32 cycles/ day
spray hours.
2000 cycles
Data sheets for electrophoretic paints
attest that they can only be applied to
Table 1. Reliability Standard for imagers destined for automotive applications.
metals because the whole of the part to be
coated must form either a cathode or an-
edge contact
4
and hence has the same is very cost-effective compared with other
ode in the electrochemical cell. Fortunate-
inherent reliability. Because the act of pen- wafer level packaging solutions.
ly, because electrophoretic deposition is
etrating the bond pad exposes fresh metal
potential rather than current driven, it was
at the circumference this solution obviates electrophoretic materials
found that semiconductor grade silicon
the difficulty of making Ohmic contact One of the main costs of wafer level
possesses sufficient electrical conductivity
between the RDL and the bond pad. packages is the materials set. Traditional
to allow direct coating, greatly simplifying
Via-through-pad interconnects require semiconductor materials are too expensive
the process flow. A second attribute of
passageway through the silicon wafer. for a product where the ultimate goal
the electrophoretic paints being electric
However, unlike TSVs, the opening is is a video graphics array (VGA) camera
field dependent is that the deposit laterally
purely mechanical and needs only to module priced at under $1. A solution was
spreads beyond the conductor, allowing
expose sufficient area of the bond pad to identified in the form of a product already
small gaps of insulator to be bridged. An
permit formation of the via-through-pad used in high tonnage by the automotive
example of a wiring trace with electrophop-
edge contact. Consequently, the align- industry. Electrophoretic paints are materi-
retic protection beyond the width of metal
ment accuracy and limits on pitch can be als that are deposited using the principle
track is shown in Figure 5. This provides
relaxed, since several interconnects can of electrostatic attraction. An electrocoat
the means for obtaining complete cover-
share a single opening. Because the open- system applies a direct current charge
age over the part, including the package
ings through the silicon do not have to to a metal part immersed in a bath of
sidewall.
be individual, the profile of the openings oppositely charged paint particles (Figure
The material
5
selected for this ap-
can be relaxed to a trapezoid with rounded 4). The paint particles are drawn to the
plication is an epoxy, resin-based system
corners. This eliminates one of the sources metal part and adhere to it forming an
that contains 23% solids by weight. This
of unreliability of TSVs. Finally, because even, continuous, film over every surface
product is not a dangerous preparation
via-through-pad interconnect is based on and in every crevice and corner, until the
according to directive 1999/45/EC. Ap-
polymer technology with a single RDL, it coating reaches the desired thickness. At
plication is by a cathodic system. In the
final design a single layer of electrophoretic
Test Conditions Readout Points
Preconditioning 3x lead-free reflow cycles Completion
High temperature storage 150ºC 1,000hrs pass/fail
Low temperature storage -40ºC 1,000hrs pass/fail
Damp heat storage 85ºC, 85%RH 168hrs pass/fail
Autoclave 121ºC, 100%RH, 2atm 168hrs pass/fail
Thermal shock -40ºC to 125ºC, 10min dwell, <7sec transition 1,000cyc pass/fail
Thermal cycling -30ºC to 125ºC, 30min dwell, <1min transition 1,000cyc pass/fail
Free fall drop 30x 1.5m all faces on to concrete Completion
Mechanical shock 5x all 6 axes 1,500g, 2,000g and 2,500g pass/fail
Variable frequency vibration 20 to 2000 Hz, 8gs, 15 mins, each direction Completion
Table 2. Automotive board level specification environmental tests for microelectronic components.
20 – Global SMT & Packaging – June 2009
www.globalsmt.net
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