Cost reduction of wafer level packaging by using established materials from non-electronics industries
that have not yet been satisfactorily solved.
Points of weaknesses in the design include
dielectric and conductive coating of the
side walls of a high aspect ratio pipe; the
90 degree bends at the top and base of the
pipe that the redistribution layer (RDL)
must traverse and maintain connectivity
during thermal cycling; and the difficulty
of cleaning the back of the bond pad so
! !
!
the RDL can make an Ohmic contact
Figure 2. Formation of a wafer-level cavity package. Left—the device wafer containing five die. Middle—appli-
when it is the bottom of a long narrow
cation of the seal material to form a picture frame around the perimeter of each die. Right—attachment of a lid pipe. A further consideration is that be-
material to seal the cavity over each die. Singulation frees the packaged die from the wafer. Source: Tessera.
cause the TSVs extend through the entire
thickness of the die it is impossible to place
assembly to yield individual die, each with
any semiconductor circuitry in the region
a cover over the delicate image sensor area.
of the bond pads. A decrease in silicon
This process is illustrated schematically in
utilization results in an increase in die size
Figure 2.
and a direct impact on the component
Wafer-level packaging provides two
price.
benefits that have great value for image
A modern wafer level package for
sensors. Firstly, the dies are protected from
image sensors is typified by the SHELL-
the very first step of the assembly process,
CASE® MVP solution, an example of
Figure 3. Image sensor packaged at the wafer level
and provided with a ball grid array interface to sim- so that yield loss from contamination is
which is shown in Figure 3. In this design,
plify and cheapen attachment to a printed circuit
eliminated. The second benefit is that it
connection between the bond pads and
board. Source: Tessera.
is possible to provide the packaged die
the ball grid array is by a via-through-pad
with a ball grid array (BGA) interface. This
technology. This implementation has few
permits the camera module to be soldered
restrictions on the bond pad size, pitch
to the main printed circuit board of the
or location, making it directly compat-
product at the same time as all the other
ible with the majority of existing CMOS
semiconductor and passive components.
imagers. The dicing lanes can be as narrow
Owing to these benefits, it is forecast that
as the silicon design rules allow, which
by 2011 more than 50% of all imagers will
helps to maximize the number of die per
be enclosed in a wafer-level package with a
wafer and decrease unit cost. The packaged
BGA interface
2
.
imager thickness is approximately 500 µm,
making it imminently suitable for electron-
Wafer level package interconnects
ics products where the current fashion is
One challenge of wafer level packaging
for extreme thinness.
of image sensors is making contact to the
The via-through-pad interconnect
bond pads, which are on the front face
superficially resembles a TSV, but the dif-
of the die and inaccessible underneath
ferences are important and have profound
the glass cover that protects the optically
implications for the product cost and reli-
active area of the die. An obvious solution
ability. In this contact, the RDL penetrates
is through silicon via (TSV) technology.
through the thickness of the bond pad to
!
There are many variations of TSVs, a
form a circumferential edge contact. This is
Figure 4. Principle elements of a cathodic electro-
common implementation being a hollow
structurally identical to the well-established
coating system. The part to be coated is immersed in
a bath and forms the cathode electrode in a circuit
pipe, with near-vertical sidewalls, machined
to which the electrophoretic paint is attracted. Gas through the thickness of the silicon. Onto
evolution occurs from both the anode and cathode as
the sidewalls of the pipe is applied a dielec-
a by product of the coating process.
tric film overlaid with conductive metal.
The through via is machined by deep reac-
with discrete ceramic packages. As the tive ion etching using the Bosch process
3
.
completed packages are diced directly from Despite being technically possible for
the wafer, the chip and the package dimen- many years, TSVs have never been adopted
sions are one and the same. This attribute in high volume manufacture. There are
is unique among semiconductor packaging several reasons for this, notable amongst
solutions and hence wafer level packages which are the high capital cost of the
are sometimes also referred to as “chip- equipment required, the slow etch rate of
sized packages.” silicon, which curtails throughput, and
Figure 5. Electrophoretic paint applied to a wiring
A wafer-level cavity package for an im- the complexity of the additional process
trace on a dielectric substrate. As the coating in-
age sensor is achieved simply by applying a steps to fabricate conductive vias that are
creases in thickness it grows laterally to seal the edges
picture frame of adhesive around each die, insulated from the silicon through which of the wiring trace and may coalesce to completely
attaching a glass wafer and then sawing the they pass. There are also issues of reliability
cover the dielectric material. Source: Tessera.
www.globalsmt.net Global SMT & Packaging – June 2009 – 19
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