Title
PiP, PoP and PuP—Package with package construction options
Joe Fjelstad
PiP, PoP and PuP—
Package with package
construction options
Since the beginning, all IC packages benefit of co-design.
have been designed to perform the basic The path to the myriad devices that are
tasks of interconnecting and protecting in use today was anything but straight line.
the semiconductor die and making it Packaging and interconnection solutions
useful for interconnection at the next have caromed back and forth across in
level. Electronic packaging technology has interconnection horizon over time, from
diversified explosively since the first ICs early surface mount to through hole, back
were produced, providing evolutionary and to surface mount and now on to 3D. Lead
sometimes revolutionary advantages with formats on the IC packages have gone from
each new development. By way of example, circular to square and from two and four
when ICs first hit the market, there were sided peripherally leaded packages to area
fundamentally just two package types, the array devices having lead sizes, shapes and
flatpack structure of Texas Instruments and pitches that create a cacophony of options
the dual-in-line (DIP) structure of Fairchild, that, paradoxically, rather than improving
the two pioneering companies of integrated the design process actually and ultimately !
circuit technology (though Fairchild did removes options by forcing the designer to
A Package under Package (PuP) structure using
use TO can packaging for some if the create less than optimum designs caused by
legacy IC components (in this case a J-leaded pack-
company’s very earliest ICs). the excess of options which are all in play.
age and a TQFP). In construction the smaller device
is precision bonded to the undercarriage of the larger.
Today, by some estimates, more than There is an arguably more logical ap-
Both devices retain their compliant lead structure,
1500 semiconductor packaging structures proach possible, one that looks deeper and
while significantly reducing real estate requirements.
have been proposed, designed or produced wider into the challenges of interconnec-
for the IC design engineer to choose from tions and which could truly liberate design
for his or her particular unique design. To by, paradoxically, locking the design down
built in the mid to late 1980s. Package on
provide of a quick contrast, in the 1970s, to a standard grid. This is a topic that has
package was also used for some memory
there were perhaps 30 different options been covered here before and one that will
chips by designers looking to get more
and for the most part those early devices be covered again in the not too distant
electronics into less space with DIPs and
were designed to be complimentary to the future. In the meantime, the name of the
that was followed by TSOPs and then by
PCB design process. The number 1500 game is space saving in all three dimen-
FBGAs.
is unquestionably large, but it is also, sions of space. This is where the acronymic
Package in Package or PiP was devel-
in a way, a testament to the increase in title of this month’s column comes into
oped as an alternative to KGD. Once the
importance that the IC package has come focus.
package reached chip size or chip scale,
to enjoy. It is now a generally recognized While it might seem new to some,
their applicability to addressing the chal-
fact among designers that the IC package 3D package technology has roots that
lenge became apparent to many designers
is more and more frequently the gating reach back around a quarter century if not
and they became useful in the creation of
design element relative to electronic system farther. The first work of personal experi-
the System in Package (SiP) structures that
performance. Unfortunately, each new ence, which was covered in the column a
have become very popular of late. SiPs have
solution is too often generated in isolation few years back, was a PoP or package on
come to be seen as a viable alternative to
with little evident concern for what comes package structure comprised of a an UV-
SoC or system on chip due to their shorter
next or thought given to the potential EPROM mounted on a multichip package
time to market and lower startup cost and
4 – Global SMT & Packaging – March 2009
www.globalsmt.net
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