PoP: An EMS perspective on assembly, rework and reliability
Background
reflowed in the carrier. During assembly ent fluxes for package on package assembly
For handheld portable devices, space
of the main circuit board, the pre-stacked to determine which gave the best results in
restrictions have long been a significant
components are picked out of the carrier terms of assembly yield and reliability. In
design challenge. In an effort to enable
and placed onto the circuit board, which addition, a relatively new class of materi-
increasing functionality in smaller form
has been screened with solder paste. The als, dippable solder pastes, was studied to
factors, components targeted at portable
entire assembly is then reflowed to com- determine if improvements in yield and/
applications have been decreasing in size
plete the process. The pre-stacking process or reliability could be achieved. Histori-
for many years. At first the size reductions
is illustrated in Figures 1 through 4. cally, package on package components have
were achieved by using chip scale pack-
The second approach is the focus of been assembled by performing the dipping
ages rather than lead frame devices, which
this study, as it requires only one pass operation using flux. However, package on
reduced the amount of board real estate
down the SMT line rather than two, as package components are known to warp
required. The next significant trend in
would be necessary for the pre-stacking during reflow
2,3
, and opens can result in
size reduction was reducing the pitch of
process. It also allows flexibility in which the joints between the upper and lower
the chip scale packages, allowing the same
upper and lower package are used up to package. It is hoped that the yields can
number of I/O in a smaller space. Package
the time when the main circuit board is be improved through the use of dippable
pitches decreased from 0.8 mm to 0.65
assembled. This process involves screening solder paste—more material will be trans-
mm, then 0.5 mm and 0.4 mm. This trend
the board, then placing the components ferred to the ball, which should help fill
continues, with wafer level CSP pitches as
in the conventional way, including the bot- any spaces between the ball and pad as the
small as 0.3 mm currently being proposed.
tom package of any stacked devices. The components warp during reflow and may
However, there are practical limits on
upper package(s) of any stacked devices reduce the incidence of opens.
the form factor reduction that is possible
are then picked and dipped in either flux Accelerated thermal cycling was se-
by pitch reduction alone. More recently,
or solder paste, then placed on top of the lected as the reliability test method. Many
a trend towards integrating even more
lower packages. The entire assembly is then previous studies of package on package
functionality into a package by stacking has
reflowed, forming both layers of joints in assembly have assessed reliability through
emerged. There are two key approaches to
one reflow pass. This process is illustrated drop testing
4,5
, which is more relevant to
stacking—the first entails stacking two or
in Figures 5 through 7. the majority of current applications for
more dies within a single package using
This study aimed to investigate differ- handheld, portable applications. However,
wire bonding and sometimes flip chip
attach, and the second entails stacking
two or more packages (each containing
one or more dies) on a printed circuit
board. While from an EMS perspective
components with die stacked inside a CSP
are easier to implement—the component is
placed, reflowed, and reworked if necessary
in the same way as a conventional CSP—
there are yield and supply chain advantages
to multi-package stacking that make this
approach compelling in many cases.
Figure 5. On-board stacking step 1—lower package placement.
Multi-package stacks generally take one
of two forms—stacks of two or more similar
components, like stacked memory pack-
ages
1
, and stacks of two or more dissimilar
components, such as a logic package with
a memory device stacked on top. In some
cases, the devices may be delivered to
the board assembly location pre-stacked,
in which case they are handled much
the same way as any other component.
In other cases, the individual packages
comprising the stack are delivered to the
assembler and need to be stacked as part of
the assembly process.
Figure 6. On-board stacking step 2—upper package dip and placement.
The stacking process may be carried
out in a pre-stacking operation prior to
the assembly of the main circuit board,
or it may be carried out directly on the
circuit board during the SMT process. The
pre-stacking process involves placing the
lower packages in a carrier then dipping
the upper package(s) in flux or solder paste
and placing them on top of the lower pack-
ages. The pre-stacked components are then
Figure 7. On-board stacking step 3—assembly reflow.
www.globalsmt.net Global SMT & Packaging – March 2009 – 17
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