APPLICATIONS EUV LITHOGRAPHY
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collector mirror up to at least the 40W power levels currently being generated. Cymer has recorded around 2 per cent conversion efficiency with its pre-pulse laser and 4 per cent on solid targets in the lab. ‘The trick is to maintain CE when firing at moving droplets at 50kHz,’ says Farrar. ‘The tin droplets move across the chamber at 30m/s and you have to hit them with two laser beams at about 50,000 times per second. If you don’t hit them dead-on every time, you lose some CE. It’s a different story being able to hit a solid stationary target and being able to hit droplets at this rate. That’s a large part of the challenge.’
Mask technology
Investigations also continue into fabricating better EUV reticles or masks. ‘The system is based on internal reflections between surfaces, one of which is the mask,’ says Kurt Ronse, of Imec, a research institute working on the infrastructure of EUV. ‘That’s not a problem, except
that a photomask used in 193nm or 248nm lithography will normally have a pellicle, a thin membrane a few millimetres away from the critical pattern, which keeps particles from falling onto the mask. In EUV you can’t use a fixed pellicle because of the nature of the radiation.’ Defects will be replicated
throughout every die and every wafer printed with that mask, so it’s important to keep them to a minimum. One method being investigated is using dual pods, where an inner pod serves as a pellicle. The inner pot is removed during the exposure and then mounted again until the next exposure, so there’s always a short period where the mask is unprotected. Defects can also be introduced during fabrication and defects a few nanometres thick can create printing errors.
Another critical issue lies in the
processing and the resist chemistry of EUV lithography, in the sense that it’s difficult to reach the resolutions EUV
promises (EUV is currently targeted at sub-20nm feature sizes). This will have to advance before EUV can become a commercial technology.
Chip makers need EUV lithography
The goal for EUV sources is 250W of power, but chip manufacturers can use EUV scanners and derive big benefits at lower power. Eric Meurice, CEO of ASML, said that once EUV proves itself at a throughput of 60 wafers per hour it will replace immersion lithography in the critical layers at the 14nm node. The resolution capability of these EUV scanners is so much better than immersion lithography because of the shorter wavelength. This means that, for a particular process layer, fewer masks are needed – a significant cost saving.
‘The industry, the memory and logic chip manufacturers, are screaming out for EUV to become available as soon as possible,’ Ronse says. ‘Up until now, chip
manufacturers have been able to fabricate smaller features with multiple patterning. This works down to the 20nm logic technology node, but moving to the 14nm node would mean a lot of the layers would require triple patterning, in some cases quadruple patterning. This requires so many lithography steps, deposition steps, and etch steps that the process becomes too complex. The industry would probably rather wait for EUV to become available for the 14nm node.’ Manufacturers are trying to make 193nm multiple patterning techniques more cost-effective, says Ronse, by relaxing some design rules and imposing more design restrictions while EUV gets up to speed. Even so, high-volume production won’t be in place until 2015 at the earliest, say most commentators – but, as Meurice said, once commercially available, EUV will provide scaling capabilities, i.e. shrinking feature sizes, that could last another 10 or 15 years. l
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www.avantes.com Electro Optics
213x130mm_3.indd 2 14 ELECTRO OPTICS l FEBRUARY 2013
www.electrooptics.com 12/4/2012 3:36:15 PM
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