news review Graphene potential closer
RESEARCHERS have developed a method of manufacturing transistors with graphene that could lead to a consistent and viable manufacturing process for a material that has been showing promise for many years. Graphene, a one-atom-thick layer of graphitic carbon, has attracted a great deal of attention for its potential use as a transistor that could make consumer electronic devices faster and smaller. But the material’s unique properties, and the shrinking scale of electronics, also make graphene difficult to fabricate on a large scale. The production of high-performance graphene using conventional fabrication techniques often leads to damage to the graphene lattice’s shape and performance, resulting in problems that include parasitic capacitance and serial resistance.
Now, researchers from the California NanoSystems Institute at UCLA, the UCLA Department of Chemistry and Biochemistry, and the department of materials science and engineering at the
UCLA Henry Samueli School of Engineering and Applied Science have developed a successful, scalable method for fabricating self-aligned graphene transistors with transferred gate stacks.
By performing the conventional lithography, deposition and etching steps on a sacrificial substrate before integrating with large-area graphene through a physical transferring process, the new approach addresses and overcomes the challenges of conventional fabrication. With a damage-free transfer process and a self-aligned device structure, this method has enabled self-aligned graphene transistors with the highest cutoff frequency to date — greater than 400 GHz.
The research demonstrates a unique, scalable pathway to high-speed, self- aligned graphene transistors and holds significant promise for the future application of graphene-based devices in ultra–high-frequency circuits. Authors of
ASML announce results ASML announced the investment in
450mm by manufacturers signalling a change in industry dynamics and now confirms its global strength with positive fiscal results. The company has confirmed steady sales for the remainder of the year and is on track for 2012 second half sales between EUR 2.2 and 2.4 billion.
“We executed H1 2012 as planned and expect sales to remain steady in the second half,” said Eric Meurice, President and Chief Executive Officer of ASML. “The second half revenue level is expected to be between EUR 2.2 billion and 2.4 billion and looks sustainable by an increase of NAND memory critical layer systems shipments, stability of DRAM memory systems sales, and slower 28/32 nm Logic in the second half compared with the first half. The exact level of sales achieved in the second half will depend on the strength of NAND pick up, itself fueled by ultrabook PCs and smartphone ramps.”
For the third quarter 2012, ASML expects net sales of about EUR 1.2 billion, gross margin of about 43 percent, R&D costs at EUR 145 million and SG&A costs at EUR 60 million. To date they have shipped 30 TWINSCAN NXT:1950i systems. Also in
the research include UCLA chemistry postdoctoral scholars Lei Liao and Hailong Zhou; UCLA chemistry graduate students Lixin Liu and Shan Jiang; UCLA materials science and engineering graduate students Rui Cheng, Yu Chen, YungChen Lin and Jinwei Bai (now a research scientist at IBM); UCLA associate professor of materials science and engineering Yu Huang; and UCLA associate professor of chemistry and biochemistry Xiangfeng Duan.
this quarter A TWINSCAN NXT:1950i has exceeded the productivity milestone of more than 5,100 wafers in a single day, 600 wafers more than the previous record.
“On the technology front, we expect to ship the first of the NXE:3300,” Meurice said. “Our production-capable Extreme Ultraviolet (EUV) system, by the end of this year or early next year and the rest of our 11 unit order in 2013. These tools will be used for process development. We are furthermore making progress in preparing EUV lithography for 2014 device production, evidenced by customer commitment to purchase four additional production systems for delivery in 2014. This commitment is enabled by the data gathered on source power increase and by steady performance of the six units already in the field,”.
The computational lithography unit Brion delivered enhancements to its leading Mask 3D models and applications, which are required at the 20 nanometer node and below. The full accuracy of the Brion Mask 3D models can now be realized with virtually zero incremental computational cost as well as substantially less accurate thin mask models.
With regards to productivity of the EUV source, 50 Watt power capability has been repeatedly demonstrated at a supplier and 105 Watt concept potential has been confirmed in lab experiments, supporting the roadmap to volume production systems starting at 70 wafers per hour. In situ experiments on the NXE:3300 will however still be necessary for full confirmation.
ASML announced a co-investment program in which customers will potentially contribute up to EUR 1.38 billion over the next 5 years to accelerate the development of 450mm wafer platform and the next generation of EUV systems, expected to enter volume production in the second half of this decade.
Issue III 2012
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