news review
Self assembly accelerator for Tokyo Electron at imec
IMEC and Tokyo Electron (TEL) have announced that they will accelerate their Directed Self-Assembly (DSA) activities at imec’s recent 300 mm fab-compatible DSA process line. Over the past two years, both companies have been actively engaged in DSA development. Based on results achieved on imec’s 300 mm DSA process line, imec and TEL will expand their focus to explore DSA as viable patterning technique for 2x and beyond technologies.
Recent evaluations have demonstrated the feasibility of DSA to enable frequency multiplication through the use of block copolymers. Line features as small as 12.5 nm and 25 nm contact holes have been patterned on 300 mm substrates at imec using pre-patterned lithography followed by DSA. In recent experiments using pre-patterned EUV holes interfaced to ASML’s NXE:3100, DSA repaired defective features, lowered line edge roughness (LER) and improved critical dimension (CD) uniformity.
For widespread DSA implementation, lower defect levels are required, and DSA needs to be integrated into existing flows. Imec and TEL are investigating various integration scenarios for line and hole patterning. Comprehensive evaluations to understand material and process interactions on CD uniformity, LER and defect levels are planned.
To push the capabilities of DSA beyond lab-scale environments, one of the world first 300 mm fab-compatible DSA process lines all-under-one-roof was recently implemented in imec’s 300 mm clean room fab. In addition to TEL’s especially configured DSA coater/developer managing gallon-sized quantities of block copolymers, and TEL’s dedicated etch system supporting the DSA pattern transfer, imec has the necessary metrology, cleaning and pattern transfer toolsets. To complete the DSA process line and accelerate R&D on DSA at imec, TEL will provide imec with new hardware
imec looks at future gate options
IMEC is successfully testing and evaluating various options for further transistor scaling using high-k dielectrics and metal gates in a replacement metal gate (RMG) integration schema. Although RMG technology is inherently more complex than gate-first integration, it has a number of advantages that allow increasing the device performance and that widen the choices in terms of high-k and metal gate materials.
One of the current challenges to enable further device scaling is the choice of gate dielectric and gate electrode. For the gate electrode, the key parameters to consider are the work function, resistivity and compatibility with CMOS technology. Further scaling also requires continued improvement of the channel mobility, adding the options for improved stress management and also reliability control as a first-order consideration in the choice of materials and processes.
In the industry, the RMG approach is
rapidly becoming the integration scheme of choice, and an alternative for the gate- first approach. In RMG, the high-k gate dielectric is deposited in the beginning of the flow or just prior to gate electrode deposition and the electrode is deposited after the formation of the junctions.
A clear advantage is the enhancement of the channel stress in shorter devices because of the dummy-gate removal, an intrinsic step in RMG flow. RMG also allows metal gate processes with a lower thermal-budget, which broadens the range of material options for work-function tuning and reliability control. Advantages are a lower gate resistance compared to gate- first, important for RF CMOS, and more room for mobility improvement.
Imec and its partners have had an important role in the introduction of high-k metal gate processes, building a strong expertise and track record. With the eye on further scaling to sub-20nm technology nodes, they are now evaluating RMG
technology for different application, materials selection and engineering, and compatibility with advanced modules and device architectures, for which we collaborate with the major tool suppliers. For our partners, we conduct fair comparisons of options, and in-depth understanding of the physical mechanisms and techniques involved, and the chance to explore the limits in performance and reliability.
The research is performed in cooperation with imec’s key partners in its core CMOS programs Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.
Issue III 2012
www.siliconsemiconductor.net 13 within the next few months.
“With specially configured DSA coater/developer and etch systems at imec, we have the capability to explore DSA as a potential candidate for next- generation patterning technology”, commented Chung Gishi, Executive VP of Tokyo Electron Ltd. “We hope to understand the critical processes necessary to move early stage development into volume production to benefit our customers”.
“DSA continues to show much promise as part of the toolbox for advanced sub-20 nm patterning. Our collaboration with Tokyo Electron has enabled us to rapidly implement DSA processing knowledge that has been developed in academia at the group of Prof. Paul Nealey (University of Wisconsin at Madison) into a representative manufacturing environment. We are excited to extend this effort to dedicated newly developed DSA modules.
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