Special


course, ties into po wer considerations. SWaP is not specified by VME or VPX, but OpenVPX is defined to supply 120 W at 5 V and 383 W at 12 V. The challenge is that this increased po wer creates heat management issues.


While OpenVPX does not consider spe- cific temperature range or heat-flow-rate cooling strategies, the dimensions of board features such as side rail wedge mounts to facilitate conduction cool- ing are specified. Rugged and service - able OpenVPX COTS is standardized in VITA 46 and VITA 48 (VPX-REDI). Dimensional specifications for cooling are given in VITA 48.1 for convection, VITA 48.2 for conduction, as well as VITA 48.3 for liquid. Covering all cool- ing methods in one standard enables board manufacturers to offer each board design with various cooling options.


Although all forms of heat management are supported by OpenVPX, conduction cool- ing is becoming the method of choice for ruggedized military and aerospace applica- tions. Air is often contaminated or unavail- able, and convection is often inadequate.


Bus characteristics Common bus used


Typical bus bandwidth Bus minimum pin count Standard max bus width


Minimum bus width Bus Size Variation


Additional commonly available bus interface Bus links configurable by FMM


User-defined connector features Common user I/O pin counts


Pin arrangement in connector User I/O variation above standard pin count


Other feature sets Thermal models


Standard form factors PMC/XMC capable


Standard voltages


Forced-air and liquid cooling require fans and pumps. Mechanical de vices fail quicker than electronics and can se verely reduce MTBF belo w 200,000 hours, which is often the minimum required for mission-critical systems. The development of heat pipes that can carry more than 150 times the heat flow per volume than aluminum is increasing the popularity of conduction-cooled OpenVPX thermal management systems.


Making the connection OpenVPX connectors are a signif icant advance over VME alternatives. They pro- vide greater bandwidth, inlet power, num- ber of pins, and serviceability (Table 1). OpenVPX connectors also facilitate sys- tem-level development of VPX LRUs, to speed deployment and help maintain OpenVPX technologies’ field readiness. The MultiGig RT family of connectors, for example, provides much higher band- width, pin density, and mission-critical ruggedness than VME64x’s DIN 41612 connectors.


Specifically, 3U OpenVPX boards ha ve three MultiGig RT2 connectors (P0 – P2):


VME64x VMEbus


Supports 80 MBps for standard 64-bit VME, up to 320 MBps for the 2eSST standard


106 (approx.) 64 bit 64 bit 64 bit


100 Mb/1 GbE No


205


Low-speed pin construction with minimal GND shielding


Different module interface and user I/O “profiles” No Connector variations I/O routable by FMM


No No


No


Air/conduction cooled 6U


Yes (XMC support varies)


+3.3V, +5V,+12V,-12V,Optional (-V1,+V1,-V2,+V2)


VPX/OpenVPX on the front lines


■ P0 has 56 pins for power, addressing, system management, and other utility signals.


■ P1/P2 have 112 pins each that can be used as differential pairs or as single- ended conductors.


The 6U boards have seven connectors. P3 through P6 can be used for dif ferential pairs or single-ended signals, with one row of P3 through P6 reserved for single- ended signals. Other signals requiring coax or fiber optics can be connected through P5 or P6. Currently , coax and fiber optics for 3U boards are not pre - scribed by OpenVPX. However, they can be custom connected from the front panel.


The MultiGig RT connector’s ruggedness facilitates military 2LM. It permits boards to be removed and inserted by reason - able manual force from front handles. The MultiGig RT connector has been tested for thermal and mechanical shock, vibration, and contaminants. Through severe test- ing, pin contact resistance remains low. The MultiGig RT connector has electri - cally grounded blades adjacent to sensitive recessed pins, making it virtually impossi-


OpenVPX (VITA 65) PCI Express (PCIe)


PCIe v2.x = 500 MBps per lane, 16 lanes (PCIe v2.x = 8 GBps) 4 = 1 lane


1 lanes (1 TX diff. pair + 1 RX diff. pair) 16 lanes (PCIe v2.x = 8 GBps) 1,2,4,8,16 lane variations Serial RapidIO/10 GbE Yes


6U = 360 , 3U = 108 (varies by module profile type - important to review card selected)


Integrated controlled impedance differential pair conductors with GND shielding between each pair for improved signal integrity


Might increase depending on bus width implementation Yes - Important to evaluate profile compatibility Differential pair or single-ended pin arrangements Yes


Air/conduction/liquid cooled 6U and 3U Yes


3U = (VS2)+3.3V,(VS3) +5V,(VS1) +12V, Aux+12V,Aux-12V, Aux+3.3V


6U = (VS2)+12V,(VS3) +5V,(VS1) +12V, Aux+12V,Aux-12V, Aux+3.3V


Table 1 | A comparison of VME64x and OpenVPX (VITA 65) 24 VME and Critical Systems / Spring 2011


Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32