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The simulation was performed for 106
lated to 1012 [Figure 3 | Eye diagram w. (blue) and w/o. (red) TVS Diode located at host and at device side.]
(blue line) and without the TVS diode (red line).
The degradation in eye pattern opening is very small. Yet at the same time this approach affords a huge safety margin with respect to the USB 3.0 specification mask (magenta line).
Summary
Successful USB 3.0 design requires both error-free Signal Integrity and excellent system-level ESD performance. To meet these requirements, the ESD pro- tection device must provide excellent ESD performance and a very low device capacitance. This can be achieved using the Infineon ESD3V3U4ULC in “array” configuration combined with a clear and straightforward layout and high link quality (USB 3.0 cable).
Alexander Glas is a senior staff engineer at Infineon’s RF Protection Device group. He has been working in various positions
in RF research, development, and technical marketing for 20 years. Alexander holds an electrical engineering degree granted by the Technical University of Munich.
Infineon Technologies
www.infineon.com
ECD in 2D: See more on Infineon, which specializes in the production of the high-value computer chips found in smartphones and other devices. Use your smartphone, scan this code, watch a video:
http://bit.ly/eRJerm
bits. The eye diagram was extrapo- bits and run both with TVS
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Embedded Computing Design April 2011 | 31
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