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protection provides system-level ESD protection according to IEC61000-4-2.
For proper USB 3.0 system-level ESD protection, the ESD protection device (TVS diode) has to handle the majority of the ESD current and keep the clamping voltage as low as possible. The residual ESD stress visible for the subsequent device has to be within the limits stated for this device.
The relevant TVS diode characteristics are: f Lowest Ron
(Rdynamic
f Lowest Vbreakdown, application
) but tailored to the
A rule of thumb for Vclamp effect): Rdynamic
[Figure 2 | TLP result for the Infineon ESD3V3U4ULC dedicated for USB 3.0 SuperSpeed ESD protection.] (no snapback can be extracted by
Transmission Line Pulse (TLP) measure- ment (Figure 2).
For a safe application, Vbreakdown has to fit with the maximum applied signal level
on the protected lines. Lowest Rdynamic in combination with optimized Vbreakdown keeps residual ESD stress for the IC minimized.
Infineon produces an application tailored TVS Diode (ESD3V3U4ULC) to meet the requirements for USB 3.0 SuperSpeed ESD protection. It has an Rdynamic
of only 0.2 Ohm (typ.) and maxi-
mum reverse working voltage of 3.3 V (Vbreakdown
: 5 V min).
Clamping voltage for a 16 A ESD strike shows 9 V, which is a best-in-class result. Diode capacitance (diode versus GND) is 0.4 pF typical. ESD handling capability exceeds 20 kV without any degradation. The 16 A TLP test pulse fits very well to an 8 KV contact ESD strike according to IEC61000-4-2, providing an ESD cur- rent of 16 A @ the 30nsec point.
To complete the system design, separate TVS diodes are required to protect the additional USB 2.0 link. These diodes have to provide a slightly higher reverse working voltage/breakdown voltage to handle the Full-Speed and the Low-Speed mode. The Infineon ESD5V3U1U and ESD5V3U2U series serve a minimum
Figure 2 | TLP result for the Infineon ESD3V3U4ULC dedicated for USB 3.0 SuperSpeed ESD protection.
reverse working voltage of 5.3 V (Vbreakdown
tance of 0.4 pF typical.
Simulation results Signal Integrity simulations of the entire USB 3.0 SuperSpeed link (Figure 1) with and without ESD protection were per- formed, based on the specification and layout rules described above. TheUSB3.0
: 6 V min) and a diode capaci-
cable was specified to maximum three- meter length. TVS diodes were placed at the host and at the device side.
For simulation, Infineon implemented TX de-emphasis and RX-equalization according to the USB 3.0 compliance test standard parameters. The eye pattern (Figure 3) of the SuperSpeed signal was checked after the RX equalizer.
Figure 3 | Eye diagram w. (blue) and w/o. (red) TVS Diode located at host and at device side.
30 | April 2011 Embedded Computing Design
www.embedded-computing.com
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