In a perfect system without limitation in bandwidth an eye diagram measurement of Signal Integrity would be perfectly open. In a real system, the TX and the RX impedance in combination with parasitic capacitance at both cable ends (either inside the USB 3.0 transceiver and/or externally on the PCB) limits the signal rise/fall time. External parasitics can be caused by unmatched PCB lines, the USB 3.0 connector, or other shunt capaci- tors. The low pass frequency response of the USB 3.0 cable also has to be taken into account. Changing the signal by a dedicated equalization on the TX and RX side compensates for attenuation of the high frequency content.
The SuperSpeed and the USB 2.0 trans- mission link work with differential coupled 90-Ohm lines. Signal reflections caused by impedance mismatch inside the link have an impact on Signal Integrity. To avoid this the entire layout, including the USB 3.0 cable, should be impedance matched to 90-Ohm differential.
To keep the “impair skew” as small as possible and match electrical delay, all dif- ferential coupled lines (including those in the USB 3.0 cable) have to have the same
length. High impair skew leads to common mode signal generation, which can cause problems for EMI testing. Signal Integrity will suffer as well. A proper impedance matched layout can avoid these issues.
Layout considerations for the USB 3.0 SuperSpeed and USB 2.0 link Key design considerations for the entire USB 3.0 link include:
f Fully impedance matched 90-Ohm differential design approach for all PCB lines and interconnection cables.
f NON-differential coupled lines should be minimized, as they have significant impact on the opening of the eye pattern.
f A line width of 0.3 mm and a line gap of 0.2 mm between the differential lines are desirable to minimize loss and be robust enough for PCB manufacturing. Dielectric height would be 0.2mm (FR4, er
ESD protection for USB 3.0 SuperSpeed USB operates at a funda- mental frequency up to 2.5 GHz. For high Signal Integrity, rise and fall time of the data signal has to be very fast. The 3rd or even the 5th harmonic has to be handled without significant attenuation. What’s required is a state-of-the-art semiconductor process to minimize parasitic effects to achieve fast switch- ing times. The drawback of these min- iaturized semiconductor structures is the weakness regarding overvoltage caused by an ESD strike. ESD prevention with on-chip ESD protection causes parasitic effects (parasitic capacitances), adds expensive chip area, and will never reach system-level ESD performance.
=4).
f Minimizing impair skew by identical delay (line length) between the positive and the negative line (including the USB 3.0 cable) of the differential coupled link.
A very cost-effective approach is to combine an internal ESD protection structure (integrated in the USB 3.0 transceiver) with a robust, high-current application circuit for external ESD protection implemented on the PCB. The internal ESD protection structure enables device level protection (for example, HBM JEDEC JESD 22-A115), which is important for device handling during development, production, and board assembly. The external ESD
Figure 1 | USB3.0 – Physical link including ESD protection at the host and at the device.
www.embedded-computing.com Embedded Computing Design April 2011 | 29
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