Rising to the
USB 3.0 challenge: Smart design achieves high-speed signal integrity
By Alexander Glas
A particularly tough game of tug-of-war may come to mind for engineers confronted with the rigorous technical specifications of an ultra fast data link that is backward compatible to much-lower-speed predecessors. Alexander describes an approach to meeting these challenges.
The long predicted convergence of the computer and consumer electronics industries has arrived. Driven by increasing consumer use of large digital music libraries, digital image files, and high-definition video, we are seeing a new generation of technology standards reach the market. One such standard is the Universal Serial Bus (USB) 3.0 speci- fication, which features a SuperSpeed data transfer rate of nearly 5 GBps.
At CES 2011, the USB Implementers Forum announced that 165 USB 3.0 devices had been certified, represent- ing a tenfold jump from the number of certified devices just one year earlier. And the market forecast firm InStat predicts that by 2013 the number of SuperSpeed USB devices shipped will reach one billion (25 percent of the total USB market).
USB evolution Introduced in 1996, USB hit the streets with data rates of 1.5 Mbps in Low-Speed (LS) mode and 12 Mbps in Full-Speed (FS) mode. In 2000, USB 2.0 added a High-Speed (HS) mode operating up to 480 Mbps and remained downwards compatible to both the LS and FS modes.
[Figure 1 | USB3.0 – Physical link including ESD protection at the host and at the device.]
The USB 3.0 specification released in November 2008 supports all USB 2.0 modes (HS, FS, LS) and the new SuperSpeed 5 Gbps data link. The SuperSpeed link works with separate differential data lines for download (Host => Device, called TX direction) and for the upload in RX direction (Device => Host). See Figure 1.
The combination of USB 2.0 function- ality and the new SuperSpeed mode requires a new cable construction to
28 | April 2011 Embedded Computing Design
serve three differential coupled signal lines (TX+/Tx-, RX+/Rx-, and D+/D-), along with a Vcc and GND line. Serving a high cutoff frequency without interac- tion between the adjacent differential coupled line pairs presents yet another design challenge.
Designers need a new connector shape to handle all of these lines, one compatible with the USB 2.0 connector. Close proximity of the lines results in a high probability for Elecrostatic Discharge (ESD) strikes on the SuperSpeed lines at the host and at the device.
Ultra-high-speed data transmission systems also require high Signal Integrity, especially at the receive side. Thus it is important to achieve a low bit error rate (for example, a USB 3.0 SuperSpeed bit error rate of 10-12
is typical).
www.embedded-computing.com
Strategies | Small Form Factors
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