The standard data width of a DRAM bus is 64 bits. When writing data to memory the controller generates eight additional check bits; their value is determined via XOR operation using different parts of the 64-bit data word. During reading, these check bits are recalculated and compared with the previous values. The bit-by- bit comparison of the eight stored check bits with the eight newly generated check bits is called a syndrome. It provides informa- tion on whether a bit is corrupted and identifies the affected bit. Correcting it is no longer a problem, because simply inverting the corrupted bit restores the correct data.


There are various ways to generate the check bits. Modern ECC codes can correct each DQ error within the 64-bit wide string, identify any combination of 2-bit errors, and in most cases also detect multibit errors.


Thanks to highly sophisticated algorithms, the latest chipsets are even capable of recognizing the failure of an entire DRAM and correcting it, as long as the DRAM is no more than 4 or 8 bits wide. The code can distinguish unusual DQs, as long as they belong to the same DRAM chip. Generally referred to as chip- kill, this method is the most advanced form of error correction found in commercial platforms today.


[Figure 1 | 72-bit DRAM module – read operation]


ECC memory modules must support a data width of 72 bits. Therefore, ECC support requires not only eight, but nine blocks of 8-bit wide DRAM modules per rank, and the DIMM socket must have room for 11 additional data signals (8 DQ, DQS, DQS#, and DM), as Figure 1 indicates. The extra costs for this additional DRAM module, the infrastructure on the motherboard, and the slightly reduced performance of ECC-enabled systems were reasons why ECC technology has so far failed to prevail in platforms with large production runs such as desktop and note- book systems, where cost is one of the most important criteria of success. ECC is primarily being used in servers and workstations to achieve high MTBF values and increased reliability.


With the IT industry’s transition from workstations to high- performance notebook platforms it has become necessary to implement ECC technology in compact PCs. This change has also boosted the development of energy-efficient memory con- trollers that are designed specifically for notebook platforms while supporting ECC functionality.


The arrival of these controllers has given the embedded computing industry what it has been waiting for: a reliable, economical, and stable platform incorporating the increased levels of data security automation and embedded applications demand. With DRAM structures getting smaller and smaller while process innovation cycles become shorter and shorter, the adoption of new technologies into production becomes increasingly diffi- cult. The risk of single-cell failures in new DRAM technologies below 50 nm is higher than ever before. As a result of smaller charge loads for information storage and the ever-shrinking distance between the bit lines, pattern-dependent bit failures are getting more common. At the same time, it is not possible to extend the test times for these ever-denser chips accordingly. Susceptible cells that fail at high temperatures when the infor- mation in the cells is particularly predisposed to data loss are costly to sift out reliably.


www.embedded-computing.com Figure 1 | 72-bit DRAM module – read operation


Rising data transfer rates as a result of the rapid transition of DDR3 1066 to 1333 and 1600 (with the next speed levels already within sight) increase the risk of pattern- and placement- dependent coupling effects that interfere with the transfer of single-bit data. PCBs are still produced from conventional FR4 material with large tolerances, so the design of reliable systems is becoming increasingly difficult.


However, ECC technology allows manufacturers to regain some of the security features lost over recent years. For industrial applications that do not tolerate any corrupted data or system crashes, and in view of the fact that standard-sized modules cannot be integrated into the more compact embedded plat- forms, the new DDR3 SO-UDIMMs with 72-bit data width for ECC support should be considered. SO-UDIMMs, so-called to distinguish them from the 64-bit wide SODIMMs, are sized identically to SODIMMs and have the same mechanical design of the base but use a different pin-out. Because of the limited number of pin-outs at the connectors, SO-UDIMM and SODIMM are not pin compatible. This lack of compatibility has split the market between low-cost, low reliability SODIMM platforms and highly reliable platforms with SO-UDIMM layout. Thanks to the official JEDEC standard and industry support via the latest chipsets a clear trend towards the use of SO-UDIMMs with ECC for critical applications is emerging. Because the module is no longer a proprietary solution but a widely standardized mass product, low-cost availability is ensured. Swissbit, for instance, offers DDR3 SO-UDIMMs with capacities of 1 to 4 GB and speeds up to DDR3-1333 (Figure 2).


[Figure 2 | DDR3 SO-UDIMMs in 1 GB to 4 GB and with speeds up to DDR3-133 are available from Swissbit.]


Figure 2 | DDR3 SO-UDIMMs in 1 GB to 4 GB and with speeds up to DDR3-133 are available from Swissbit.


Embedded Computing Design April 2011 | 25


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