Hyperion Ion Probe
bonds or solder bumps for
making interconnections,
whereas 3D-ICs have
dramatically shortened
interconnect lengths by
connecting circuits with
vias passing directly
through the silicon wafer.
The benefits of reduced
interconnect dimensions
include faster data transfer
rates and devices requiring
less power.
In order to attain
reliable fabrication of
TSVs, cost-effective via
inspection is required for
Figure 3: Beam size versus mill rate for the Hyperion FIB (red line) with LMIS
process and failure analysis.
FIB (blue line). The copper fill process
for these vias often results
be extensive, resulting in poor edge abruptness when milling. in unwanted sub-micron
For milling purposes, these higher current LMIS beams voids forming on the via
require some de-focus from the optimum image resolution to axis unless the precise
give a well-circumscribed beam profile. At 20 nA the LMIS electro-deposition process
FIB objective lens is often defocused marginally to pull in the is found for the particular Figure 4: Deep cross-sectional analysis
beam tails, while increasing the d
50
(beam diameter containing via dimensions chosen.
of a “Through Silicon Via,” sectioned and
imaged with Hyperion FIB.
50 percent of the current) beam width by a factor of ~1.5. At Finding these small axial
50 nA, the milling beam would need to be defocused by almost voids is best accomplished
a factor of 5 to minimize the beam tails from spherical blur. by successively removing a thin layer of material from a
Figure 3 compares 30keV LMIS and Hyperion cross-sectioned via and then imaging the newly revealed
performance, in terms of the optimum beam size (or milling face. Other artifacts of via manufacturing can require close
resolution) as a function of milling rate for a silicon target. examination of the via walls or interfacial regions, but in all
Here we use a sputter rate of 0.27 μm
3
/nC for the gallium beam cases precise removal of material is required. Mechanical
and 0.46 μm
3
/nC for the xenon beam. For a true comparison polishing alone can result in mechanical stresses and damage
of milling resolution, the blue line shows the beam width with to the vias. Broad-area ion beams lack the site specificity to
the optimum defocus for the LMIS to achieve suitable milling iteratively remove material and image the site of interest, and the
beams. Once the enhanced sputter yield is accounted for, along LMIS-FIB is too slow to remove the required material volumes
with the required LMIS FIB defocus, Hyperion shows a gain in that often exceed 10
6
μm
3
during an analysis. At 6 μm
3
/s, a 20
milling resolution at rates above ~6 μm
3
/s, equating to a gallium nA gallium beam would be an impractical, expensive solution
beam current of 20 nA. taking approximately 46 hours of instrument time.
This precipitous drop in milling resolution for the However, the example shown here has been prepared
LMIS FIB results from the large acceptance angles required with just 30 minutes of milling with the Hyperion FIB system.
for low-angular intensity ion sources. So, at these higher In this case, the via is approximately 120 μm deep and 20 μm
currents, a source with a high-angular intensity is optimal wide with void formed at the base of the via and indications
even at the expense of overall brightness. In fact, the effective that further voids would have occurred if the copper deposition
beam brightness of the Hyperion source (at the target) can be process had been completed.
maintained from pico-Amps up to many micro-Amps. Due to In the coming years, critical interconnects and vertically
an angular intensity of ~10 mA/sr, Hyperion excels at beam stacked circuitry will often need to be excavated by deep FIB
currents >20 nA, while still having the brightness and energy milling for failure analysis. Yole Développement estimate that
spread to provide <25 nm resolution for fine milling and over the next 3-4 years, the volume of 3D wafers fabricated will
imaging at 30 keV. increase 10-fold. The number of TSVs per die could be as high
The Hyperion FIB is now satisfying a broad array of as 10
5
with 10-15 wafers per die aligned and bonded to within
milling applications, which includes large-area cross-sectioning ±1 μm. New materials and fabrication processes are being
of next-generation 3D IC technologies, such as “Through- investigated for enhanced thermal management and optimal
Silicon Vias” (TSVs) [5]. TSV interconnects are thought to high-density device stacking. It is anticipated that future 3D
be the ultimate solution to overcome the space limitations devices will have active circuitry and interconnects in a stack
of Package-on-Package (POP) and System-in-Package (SiP) of silicon of up to 1 mm high. The Hyperion FIB now provides
devices. POP and SiP packages rely on standard off-chip wire a viable ion-beam technique to tackle this type of precision
20
www.microscopy-today.com • 2009 September
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